• 대한기계학회:학술대회논문집
• /
• 대한기계학회 2003년도 추계학술대회
• /
• pp.1027-1032
• /
• 2003

Thermo-mechanical behavior of flip-chip plastic ball grid array (FC-PBGA) packages are characterized by high sensitive $Moir{\acute{e}}$ interferometry. $Moir{\acute{e}}$ fringe patterns are recorded and analyzed for several temperatures. Deformation analysis of bending displacements of the packages and average strains in the solder balls for a single-sided package assembly and a double-sided package assembly are presented. The bending displacement of the double-sided package assembly is smaller than that of the single-sided one. The largest of effective strain occurred in the solder ball located at the edge of the chip and its magnitude of the double-sided package assembly is greater than that of single-sided one.

• 마이크로전자및패키징학회지
• /
• 제6권4호
• /
• pp.61-71
• /
• 1999

통신분야에서 사용주파수대역의 증가, 제품의 소형화 및 가격경쟁력등의 요구에 따라 RF 소자의 패키징 기술도 플라스틱 패키지 대신에 flip chip interconnection, MCM(multichip module)등과 같은 고밀도 실장기술이 발전해가고 있다. 따라서, 본 논문은 최근 수년간 보고된 응용사례를 중심으로 RF flip chip의 기술적인 개발방향과 장점들을 분석하였고, RF 소자 및 시스템의 개발단계에 따른 적합한 적용기술을 제시하였다. RF flip chip의 기술동향을 요약하면, 1) RF chip배선은 microstrip 대신에 CPW 구조을 선택하며, 2) wafer back-side grinding을 하지 않아서 제조공정이 단순하고 wafer 파손이 적어 제조비용을 낮출 수 있고, 3) wire bonding 패키징에 비해 전기적인 특성이 우수하고 고집적의 송수신 모듈개발에 적합하다는 것이다. 그러나, CPW 배선구조의 RF flip chip 특성에 대한 충분한 연구가 필요하며 RF flip chip의 초기 개발 단계에서 flip chip interconnection 방법으로는 Au stud bump bonding이 적합할 것으로 제안한다.

• 마이크로전자및패키징학회지
• /
• 제20권3호
• /
• pp.63-69
• /
• 2013

Package on Package(PoP)용 하부 패키지에 대해 플립칩 본딩으로 칩을 기판에 실장한 패키지와 die attach film(DAF)을 사용하여 칩을 기판에 접착한 패키지의 warpage 특성을 비교하였다. 플립칩 본딩으로 칩을 기판에 실장한 패키지와 DAF를 사용하여 칩을 기판에 실장한 패키지는 솔더 리플로우 온도인 $260^{\circ}C$에서 각기 $57{\mu}m$와 $-102{\mu}m$의 warpage를 나타내었다. 상온에서 $260^{\circ}C$ 사이의 온도 범위에서 플립칩 실장한 패키지는 $-27{\sim}60{\mu}m$ 범위의 warpage를 나타내는 반면에, DAF 실장한 패키지는 $-50{\sim}-153{\mu}m$ 범위의 warpage를 나타내었다.

• 대한기계학회:학술대회논문집
• /
• 대한기계학회 2007년도 춘계학술대회A
• /
• pp.1673-1678
• /
• 2007

The use of flip-chip type electronic package offers numerous advantages such as reduced thickness, improved environmental compatibility, and downed cost. Despite numerous benefits, flip-chip type packages bare several reliability problems. The most critical issue among them is their electrical performance deterioration upon consecutive thermal cycles attributed to gradual delamination growth through chip and adhesive film interface induced by CTE mismatch driven shear and peel stresses. The electronic package in use is heated continuously by itself. When the crack at a weak site of the electronic package occurs, thermal deformationon the chip side is changed. Therefore, we can measure these micro deformations by using Moire interferometry and find out the crack length.

• 한국재료학회지
• /
• 제17권2호
• /
• pp.91-95
• /
• 2007

Electromigration characteristics of Sn-3.5Ag flip chip solder bump were analyzed using flip chip packages which consisted of Si chip substrate and electroplated Cu under bump metallurgy. Electromigration test temperatures and current densities peformed were $140{\sim}175^{\circ}C\;and\;6{\sim}9{\times}10^4A/cm^2$ respectively. Mean time to failure of solder bump decreased as the temperature and current density increased. The activation energy and current density exponent were found to be 1.63 eV and 4.6, respectively. The activation energy and current density exponent have very high value because of high Joule heating. Evolution of Cu-Sn intermetallic compound was also investigated with respect to current density conditions.

• 한국정밀공학회지
• /
• 제20권10호
• /
• pp.183-190
• /
• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• 대한기계학회논문집A
• /
• 제28권9호
• /
• pp.1408-1414
• /
• 2004

The use of flip-chip technology has many advantages over other approaches for high-density electronic packaging. ACF (anisotropic conductive film) is one of the major flip-chip technologies, which has short chip-to-chip interconnection length, high productivity, and miniaturization of package. In this study, thermal fatigue lift of ACF bonding flip-chip package has been predicted. Elastic and thermal properties of ACF were measured by using DMA and TMA. Temperature dependent nonlinear hi-thermal analysis was conducted and the result was compared with Moire interferometer experiment. Calculated displacement field was well matched with experimental result. Thermal fatigue analysis was also conducted. The maximum shear strain occurs at the outmost located bump. Shear stress-strain curve was obtained to calculate fatigue life. Fatigue model for electronic adhesives was used to predict thermal fatigue life of ACF bonding flip-chip packaging. DOE (Design of Experiment) technique was used to find important design factors. The results show that PCB CTE (Coefficient of Thermal Expansion) and elastic modulus of ACF material are important material parameters. And as important design parameters, chip width, bump pitch and bump width were chose. 2$^{nd}$ DOE was conducted to obtain RSM equation far the choose 3 design parameter. The coefficient of determination ($R^2$) for the calculated RSM equation is 0.99934. Optimum design is conducted using the RSM equation. MMFD (Modified Method for feasible Direction) algorithm is used to optimum design. The optimum value for chip width, bump pitch and bump width were 7.87mm, 430$\mu$m, and 78$\mu$m, respectively. Approximately, 1400 cycles have been expected under optimum conditions. Reliability analysis was conducted to find out guideline for control range of design parameter. Sigma value was calculated with changing standard deviation of design variable. To acquire 6 sigma level thermal fatigue reliability, the Std. Deviation of design parameter should be controlled within 3% of average value.

• 마이크로전자및패키징학회지
• /
• 제14권4호
• /
• pp.9-14
• /
• 2007

본 연구에서는 가속화 조건에서의 비전도성 접착제가 사용된 플립칩 패키지의 열적 신뢰성에 관하여 평가하였다. 실리콘 칩에 $17{\mu}m$두께의 Au 범프를 형성하고 무전해 Ni/Au 도금과 Cu 패드의 두께가 각각 $5{\mu}m$와 $25{\mu}m$로 형성된 연성 기판을 사용하여 플립칩 패키지를 형성하였다. 유리전이온도가 $72^{\circ}C$인 비전도성 접착제를 사용하여 플립칩을 접합시킨 후 열충격 시험과 항온항습 시험을 실시하였다. 열충격 싸이클과 항온항습 유지 시간이 증가할수록 플립칩 패키지의 전기 저항이 증가하는 것을 확인할 수 있었다. 이는 Au 범프와 Au 범프 사이의 균열, 칩과 비전도성 접착제 또는 기판과 비전도성 접착제 사이의 층간 분리에 의한 것으로 사료된다. 또한 항온항습 하에서의 전기 저항의 변화가 열충격하에서 보다 큰 것을 확인할 수 있었다. 따라서 비전도성 접착제가 사용된 플립칩 패키지는 온도보다 습기에 더욱 민감하다는 것을 알 수 있었다.

• 한국마이크로전자및패키징학회:학술대회논문집
• /
• 한국마이크로전자및패키징학회 2003년도 International Symposium
• /
• pp.253-257
• /
• 2003

The low temperature flip chip technique is applied to the package of the temperature-sensitive devices for LCD systems and image sensors since the high temperature process degrades the polymer materials in their devices. We will introduce the various low temperature flip chip bonding techniques; a conventional flip chip technique using eutectic Bi-Sn (mp: $138^{\circ}C$) or eutectic In-Ag (mp: $141^{\circ}C$) solders, a direct bump-to-bump bonding technique using solder bumps, and a low temperature bonding technique using low temperature solder pads.

• 한국표면공학회지
• /
• 제36권2호
• /
• pp.214-225
• /
• 2003

Trends in microelectronics packages such as low cost, miniaturization, high performance, and high reliability made area array interconnecting technologies including flip chip, CSP (Chip Scale Package) and BGA (Ball Grid Array) mainstream technologies. Underfill technology is used for the reliability of the area array technologies, thus electronics packaging industry regards it as very important technology In this paper, the underfill technology is reviewed and the recent advances in the underfill technology including new processes and materials are introduced. These includes reworkable underfills, no-flow underfills, molded underfills and wafer - level - applied underfills.