• 제목/요약/키워드: Flip Chip bumping

검색결과 22건 처리시간 0.024초

Fine-Pitch Solder on Pad Process for Microbump Interconnection

  • Bae, Hyun-Cheol;Lee, Haksun;Choi, Kwang-Seong;Eom, Yong-Sung
    • ETRI Journal
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    • 제35권6호
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    • pp.1152-1155
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    • 2013
  • A cost-effective and simple solder on pad (SoP) process is proposed for a fine-pitch microbump interconnection. A novel solder bump maker (SBM) material is applied to form a 60-${\mu}m$ pitch SoP. SBM, which is composed of ternary Sn3.0Ag0.5Cu (SAC305) solder powder and a polymer resin, is a paste material used to perform a fine-pitch SoP through a screen printing method. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder, the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. Test vehicles with a daisy chain pattern are fabricated to develop the fine-pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si chip has 6,724 bumps with a 45-${\mu}m$ diameter and 60-${\mu}m$ pitch. The chip is flip chip bonded with a Si substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of the underfill. The optimized bonding process is validated through an electrical characterization of the daisy chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and microbump interconnection using a screen printing process.

Novel Bumping Process for Solder on Pad Technology

  • Choi, Kwang-Seong;Bae, Ho-Eun;Bae, Hyun-Cheol;Eom, Yong-Sung
    • ETRI Journal
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    • 제35권2호
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    • pp.340-343
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    • 2013
  • A novel bumping process using solder bump maker is developed for the maskless low-volume solder on pad (SoP) technology of fine-pitch flip chip bonding. The process includes two main steps: one is the aggregation of powdered solder on the metal pads on a substrate via an increase in temperature, and the other is the reflow of the deposited powder to form a low-volume SoP. Since the surface tension that exists when the solder is below its melting point is the major driving force of the solder deposit, only a small quantity of powdered solder adjacent to the pads can join the aggregation process to obtain a uniform, low-volume SoP array on the substrate, regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of $130{\mu}m$ is successfully formed.

마이크로 솔더볼의 레이저 솔더링에 관한 연구 (Research on Laser Soldering of Micro Solder-balls)

  • 강희신;서정;이제훈;김정오;신희원;김도열
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2006년도 춘계학술대회 논문집
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    • pp.661-662
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    • 2006
  • This research is on a laser soldering using the micro solder-balls used in flip chip packaging process. A laser source used in laser soldering is Nd:YAG laser(250W and 60W). Solder-balls of 100, 300, $500{\mu}m$ size are used in experiments. The laser head to deliver a laser beam and the nozzle to transfer solder-balls are manufactured to bump solder-balls. After soldering solder-balls the shear test is carried out to determine the wetting at the interface between the surface and a solder-balls With the results of solder bumping tests a laminated molding is accomplished for manufacturing the three dimensional molding.

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미세 피치를 갖는 bare-chip 공정 및 시스템 개발

  • 강희석;정훈;조영준;김완수;강신일;심형섭
    • 한국반도체및디스플레이장비학회:학술대회논문집
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    • 한국반도체및디스플레이장비학회 2005년도 춘계 학술대회
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    • pp.79-83
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    • 2005
  • IT 기술, 반도체 산업 등의 급격한 발전에 힘입어 최근의 첨단 전자, 통신제품은 초경량 초소형화와 동시에 고기능 복합화의 발전 추세를 보이고 있다. 이런 추세에 발맞추어 전자제품, 통신제품의 핵심적인 부품인 IC chip도 소형화되고 있다. IC chip 패키징 기술의 하나인 Filp Chip Package는 Module Substrate 위에 Chip Surface를 Bumping 시킴으로서 최단의 접속길이와 저열저항, 저유전율의 특성도 가지면서 초소형에 높은 수율의 저 원가생산성을 갖는 첨단의 패키징 기술이다. 이런 패키징 기술은 수요증가와 더불어 폭발적으로 늘어나고 있으나 까다로운 공정기술에 의해 아직 여러 회사에서 장비가 출시되고 있지 못한 상태이다. 이에 본 연구에서는 최근 수요가 증가하는 LCD Driver IC용 COF 장비를 위한 Flip chip Bonding 장비 및 시스템을 설계, 제작하였다.

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플립칩용 UBM (Under Bump Metallurgy)연구의 최근동향 (Recent UBM (Under Bump Metallurgy) Studies for Flip Chip Application)

  • Jang, Se-Young;Paik, Kyung-Wook
    • 한국마이크로전자및패키징학회:학술대회논문집
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    • 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
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    • pp.49-54
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    • 2001
  • This paper presents several UBM (Under Bump Metallurgy) systems which are currently used for wafer level solder bumping technology. The advantages and disadvantages of each UBM are summarized from the point of view of process compatability and interface morphological stability.

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Novel Low-Volume Solder-on-Pad Process for Fine Pitch Cu Pillar Bump Interconnection

  • Bae, Hyun-Cheol;Lee, Haksun;Eom, Yong-Sung;Choi, Kwang-Seong
    • 마이크로전자및패키징학회지
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    • 제22권2호
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    • pp.55-59
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    • 2015
  • Novel low-volume solder-on-pad (SoP) process is proposed for a fine pitch Cu pillar bump interconnection. A novel solder bumping material (SBM) has been developed for the $60{\mu}m$ pitch SoP using screen printing process. SBM, which is composed of ternary Sn-3.0Ag-0.5Cu (SAC305) solder powder and a polymer resin, is a paste material to perform a fine-pitch SoP in place of the electroplating process. By optimizing the volumetric ratio of the resin, deoxidizing agent, and SAC305 solder powder; the oxide layers on the solder powder and Cu pads are successfully removed during the bumping process without additional treatment or equipment. The Si chip and substrate with daisy-chain pattern are fabricated to develop the fine pitch SoP process and evaluate the fine-pitch interconnection. The fabricated Si substrate has 6724 under bump metallization (UBM) with a $45{\mu}m$ diameter and $60{\mu}m$ pitch. The Si chip with Cu pillar bump is flip chip bonded with the SoP formed substrate using an underfill material with fluxing features. Using the fluxing underfill material is advantageous since it eliminates the flux cleaning process and capillary flow process of underfill. The optimized interconnection process has been validated by the electrical characterization of the daisy-chain pattern. This work is the first report on a successful operation of a fine-pitch SoP and micro bump interconnection using a screen printing process.

접촉 공진 힘 현미경 기술을 이용한 플립 칩 범프 재료의 국부 탄성계수 측정 (Measurement of Local Elastic Properties of Flip-chip Bump Materials using Contact Resonance Force Microscopy)

  • 김대현;안효석;한준희
    • Tribology and Lubricants
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    • 제28권4호
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    • pp.173-177
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    • 2012
  • We used contact resonance force microscopy (CRFM) technique to determine the quantitative elastic properties of multiple materials integrated on the sub micrometer scale. The CRFM approach measures the frequencies of an AFM cantilever's first two flexural resonances while in contact with a material. The plain strain modulus of an unknown or test material can be obtained by comparing the resonant spectrum of the test material to that of a reference material. In this study we examined the following bumping materials for flip chip by using copper electrode as a reference material: NiP, Solder (Sn-Au-Cu alloy) and under filled epoxy. Data were analyzed by conventional beam dynamics and contact dynamics. The results showed a good agreement (~15% difference) with corresponding values determined by nanoindentaion. These results provide insight into the use of CRFM methods to attain reliable and accurate measurements of elastic properties of materials on the nanoscale.

3D 패키지용 관통 전극 형성에 관한 연구 (Fabrication of Through-hole Interconnect in Si Wafer for 3D Package)

  • 김대곤;김종웅;하상수;정재필;신영의;문정훈;정승부
    • Journal of Welding and Joining
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    • 제24권2호
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    • pp.64-70
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    • 2006
  • The 3-dimensional (3D) chip stacking technology is a leading technology to realize a high density and high performance system in package (SiP). There are several kinds of methods for chip stacking, but the stacking and interconnection through Cu filled through-hole via is considered to be one of the most advanced stacking technologies. Therefore, we studied the optimum process of through-hole via formation and Cu filling process for Si wafer stacking. Through-hole via was formed with DRIE (Deep Reactive ion Etching) and Cu filling was realized with the electroplating method. The optimized conditions for the via formation were RE coil power of 200 W, etch/passivation cycle time of 6.5 : 6 s and SF6 : C4F8 gas flow rate of 260 : 100 sccm. The reverse pulsed current of 1.5 A/dm2 was the most favorable condition for the Cu electroplating in the via. The Cu filled Si wafer was chemically and mechanically polished (CMP) for the following flip chip bumping technology.

Interconnection Technology Based on InSn Solder for Flexible Display Applications

  • Choi, Kwang-Seong;Lee, Haksun;Bae, Hyun-Cheol;Eom, Yong-Sung;Lee, Jin Ho
    • ETRI Journal
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    • 제37권2호
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    • pp.387-394
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    • 2015
  • A novel interconnection technology based on a 52InSn solder was developed for flexible display applications. The display industry is currently trying to develop a flexible display, and one of the crucial technologies for the implementation of a flexible display is to reduce the bonding process temperature to less than $150^{\circ}C$. InSn solder interconnection technology is proposed herein to reduce the electrical contact resistance and concurrently achieve a process temperature of less than $150^{\circ}C$. A solder bump maker (SBM) and fluxing underfill were developed for these purposes. SBM is a novel bumping material, and it is a mixture of a resin system and InSn solder powder. A maskless screen printing process was also developed using an SBM to reduce the cost of the bumping process. Fluxing underfill plays the role of a flux and an underfill concurrently to simplify the bonding process compared to a conventional flip-chip bonding using a capillary underfill material. Using an SBM and fluxing underfill, a $20{\mu}m$ pitch InSn solder SoP array on a glass substrate was successfully formed using a maskless screen printing process, and two glass substrates were bonded at $130^{\circ}C$.

Maskless Screen Printing Process using Solder Bump Maker (SBM) for Low-cost, Fine-pitch Solder-on-Pad (SoP) Technology

  • Choi, Kwang-Seong;Lee, Haksun;Bae, Hyun-Cheol;Eom, Yong-Sung
    • 마이크로전자및패키징학회지
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    • 제20권4호
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    • pp.65-68
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    • 2013
  • A novel bumping process using solder bump maker (SBM) is developed for fine-pitch flip chip bonding. It features maskless screen printing process. A selective solder bumping mechanism without the mask is based on the material design of SBM. Maskless screen printing process can implement easily a fine-pitch, low-cost, and lead-free solder-on-pad (SoP) technology. Its another advantage is ternary or quaternary lead-free SoP can be formed easily. The process includes two main steps: one is the thermally activated aggregation of solder powder on the metal pads on a substrate and the other is the reflow of the deposited powder on the pads. Only a small quantity of solder powder adjacent to the pads can join the first step, so a quite uniform SoP array on the substrate can be easily obtained regardless of the pad configurations. Through this process, an SoP array on an organic substrate with a pitch of 130 ${\mu}m$ is, successfully, formed.