• Title, Summary, Keyword: Flip Chip

Search Result 398, Processing Time 0.029 seconds

Overview on Flip Chip Technology for RF Application (RF 응용을 위한 플립칩 기술)

  • 이영민
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.6 no.4
    • /
    • pp.61-71
    • /
    • 1999
  • The recent trend toward higher frequencies, miniaturization and lower-cost in wireless communication equipment is demanding high density packaging technologies such flip chip interconnection and multichip module(MCM) as a substitute of conventional plastic package. With analyzing the recently reported research results of the RF flip chip, this paper presents the technical issues and advantages of RF flip chip and suggest the flip chip technologies suitable for the development stage. At first, most of RF flip chips are designed in a coplanar waveguide line instead of microstrip in order to achieve better electrical performance and to avoid the interaction with a substrate. Secondly, eliminating wafer back-side grinding, via formation, and back-side metallization enables the manufacturing cost to be reduced. Finally, the electrical performance of flip chip bonding is much better than that of plastic package and the flip chip interconnection is more suitable for Transmit/Receiver modules at higher frequency. However, the characterization of CPW designed RF flip chip must be thoroughly studied and the Au stud bump bonding shall be suggested at the earlier stage of RF flip chip development.

  • PDF

Development of Atmospheric Pressure Plasma Equipment and It's Application to Flip Chip BGA Manufacturing Process (대기압 플라즈마 설비 개발 및 Flip Chip BGA 제조공정 적용)

  • Lee, Ki-Seok;Ryu, Sun-Joong
    • Journal of the Semiconductor & Display Technology
    • /
    • v.8 no.2
    • /
    • pp.15-21
    • /
    • 2009
  • Atmospheric pressure plasma equipment was successfully applied to the flip chip BGA manufacturing process to improve the uniformity of flux printing process. The problem was characterized as shrinkage of the printed flux layer due to insufficient surface energy of the flip chip BGA substrate. To improve the hydrophilic characteristics of the flip chip BGA substrate, remote DBD type atmospheric pressure plasma equipment was developed and adapted to the flux print process. The equipment enhanced the surface energy of the substrate to reasonable level and made the flux be distributed over the entire flip chip BGA substrate uniformly. This research was the first adaptation of the atmospheric pressure plasma equipment to the flip chip BGA manufacturing process and a lot of possible applications are supposed to be extended to other PCB manufacturing processes such as organic cleaning, etc.

  • PDF

Flip Chip Bump 3D Inspection Equipment using White Light Interferometer with Large F.O.V. (대시야 백색광 간섭계를 이용한 Flip Chip Bump 3차원 검사 장치)

  • Koo, Young Mo;Lee, Kyu Ho
    • Journal of the Korean Institute of Intelligent Systems
    • /
    • v.23 no.4
    • /
    • pp.286-291
    • /
    • 2013
  • In this paper, in-line type flip chip bump 3D inspection equipment, using white light interferometer with large F.O.V., which is aimed to be used in flip chip bump test process is developed. Results of flip chip bump height measurement in many substrates and repeatability test results for the bumps in fixed location of each substrate are shown. Test results from test bench and those from developed flip chip bump 3D inspection equipment are compared and as a result repeatability is improved by reducing the impact of system vibration. A valuation basis for the testing quality of flip chip bump 3D inspection equipment is proposed.

Adhesive Flip Chip Technology

  • Paik, Kyung-W
    • Proceedings of the International Microelectronics And Packaging Society Conference
    • /
    • /
    • pp.7-38
    • /
    • 2000
  • Performance, reliability, form factor drive flip chip use. BGAs and CSPs will provide stepping stone to FC DCA .Growing vendor infrastructure - Low cost, high density organic substrates -New generations of fluxes and underfills .Adhesives flip chip technology as a low cost flip chip alternatives -Low cost Au stud or Electroless Ni bumps -Reliable thermal cycling and electrical performance.

  • PDF

High frequency measurement and characterization of ACF flip chip interconnects

  • 권운성;임명진;백경욱
    • Proceedings of the International Microelectronics And Packaging Society Conference
    • /
    • /
    • pp.146-150
    • /
    • 2001
  • Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe. And the cascade transmission matrix conversion was performed. The same measurements and conversion techniques were conducted on the assembled test chip and substrate at the same frequency range. Then impedance values in ACF flip-chip interconnection were extracted from cascade transmission matrix. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of SiO$_2$filler to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. High frequency behavior of metal Au stud bumps was investigated. The resonance frequency of the metal stud bump interconnects is higher than that of ACF flip-chip interconnects and is not observed at the microwave frequency band. The extracted model parameters of adhesive flip chip interconnects were analyzed with the considerations of the characteristics of material and the design guideline of ACA flip chip for high frequency applications was provided.

  • PDF

Effect of Plasma Treatment on the Bond Strength of Sn-Pb Eutectic Solder Flip Chip (Sn-Pb 공정솔더 플립칩의 접합강도에 미치는 플라즈마 처리 효과)

  • 홍순민;강춘식;정재필
    • Journal of Welding and Joining
    • /
    • v.20 no.4
    • /
    • pp.498-504
    • /
    • 2002
  • Fluxless flip chip bonding process using plasma treatment instead of flux was investigated. The effect of plasma process parameters on tin-oxide etching characteristics were estimated with Auger depth profile analysis. The die shear test was performed to evaluate the adhesion strength of the flip chip bonded after plasma treatment. The thickness of oxide layer on tin surface was reduced after Ar+H2 plasma treatment. The addition of H2 improved the oxide etching characteristics by plasma. The die shear strength of the plasma-treated Sn-Pb solder flip chip was higher than that of non-treated one but lower than that of fluxed one. The difference of the strength between plasma-treated specimen and non-treated one increased with increase in bonding temperature. The plasma-treated flip chip fractured at solder/TSM interface at low bonding temperature while the fracture occurred at solder/UBM interface at higher bonding temperature.

Flip Chip Assembly Using Anisotropic Conductive Adhesives with Enhanced Thermal Conductivity

  • Yim, Myung-Jin;Kim, Hyoung-Joon;Paik, Kyung-Wook
    • Journal of the Microelectronics and Packaging Society
    • /
    • v.12 no.1
    • /
    • pp.9-16
    • /
    • 2005
  • This paper presents the development of new anisotropic conductive adhesives with enhanced thermal conductivity for the wide use of adhesive flip chip technology with improved reliability under high current density condition. The continuing downscaling of structural profiles and increase in inter-connection density in flip chip packaging using ACAs has given rise to reliability problem under high current density. In detail, as the bump size is reduced, the current density through bump is also increased. This increased current density also causes new failure mechanism such as interface degradation due to inter-metallic compound formation and adhesive swelling due to high current stressing, especially in high current density interconnection, in which high junction temperature enhances such failure mechanism. Therefore, it is necessary for the ACA to become thermal transfer medium to improve the lifetime of ACA flip chip joint under high current stressing condition. We developed thermally conductive ACA of 0.63 W/m$\cdot$K thermal conductivity using the formulation incorporating $5 {\mu}m$ Ni and $0.2{\mu}m$ SiC-filled epoxy-bated binder system to achieve acceptable viscosity, curing property, and other thermo-mechanical properties such as low CTE and high modulus. The current carrying capability of ACA flip chip joints was improved up to 6.7 A by use of thermally conductive ACA compared to conventional ACA. Electrical reliability of thermally conductive ACA flip chip joint under current stressing condition was also improved showing stable electrical conductivity of flip chip joints. The high current carrying capability and improved electrical reliability of thermally conductive ACA flip chip joint under current stressing test is mainly due to the effective heat dissipation by thermally conductive adhesive around Au stud bumps/ACA/PCB pads structure.

  • PDF

Solid Modeling of UBM and IMC Layers in Flip Chip Packages (플립칩 패키지에서 UBM 및 IMC 층의 형상 모델링)

  • Shin, Ki-Hoon;Kim, Joo-Han
    • Transactions of the Korean Society of Machine Tool Engineers
    • /
    • v.16 no.6
    • /
    • pp.181-186
    • /
    • 2007
  • UBM (Under Bump Metallurgy) of flip chip assemblies consists of several layers such as the solder wetting, the diffusion barrier, and the adhesion layers. In addition, IMC layers are formed between the solder wetting layers (e.g. Cu, Ni) and the solder. The primary failure mechanism of the solder joints in flip chips is widely known as the fatigue failure caused by thermal fatigues or electromigration damages. Sometimes, the premature brittle failure occurs in the IMC layers. However, these phenomena have thus far been viewed from only experimental investigations. In this sense, this paper presents a method for solid modeling of IMC layers in flip chip assemblies, thus providing a pre-processing tool for finite element analysis to simulate the IMC failure mechanism. The proposed modeling method is CSG-based and can also be applied to the modeling of UBM structure in flip chip assemblies. This is done by performing Boolean operations according to the actual sequences of fabrication processes

Effect by Change of Geometries and Material Properties for Flip-Chip (플립 칩의 기하학적 형상과 구성재료의 변화에 따른 효과)

  • Kwon, Yong-Su;Choi, Sung-Ryul
    • Journal of the Korean Society of Industry Convergence
    • /
    • v.3 no.1
    • /
    • pp.69-75
    • /
    • 2000
  • Multichip packages are comprised of dissimilar materials which expand at different rates on heating. The differential expansion must be accommodated by the various structural elements of the package. A types of heat exposures occur operation cycles. This study presents a finite element analysis simulation of flip-chip among multichip. The effects of geometries and material properties on the reliability were estimated during the analysis of temperature and thermal stress of flip-chip. From the results, it could be obtained that the more significant parameters to the reliability of flip-chip arc chip power cycle, heat convection and height of solder bump.

  • PDF

A Flip Chip Process Using an Interlocking-Joint Structure Locally Surrounded by Non-conductive Adhesive (비전도성 접착제로 국부적으로 둘러싸인 인터록킹 접속구조를 이용한 플립칩 공정)

  • Choi, Jung-Yeol;Oh, Tae-Sung
    • Korean Journal of Metals and Materials
    • /
    • v.50 no.10
    • /
    • pp.785-792
    • /
    • 2012
  • A new flip chip structure consisting of interlocking joints locally surrounded by non-conductive adhesive was investigated in order to improve the contact resistance characteristics and prevent the parasitic capacitance increase. The average contact resistance of the interlocking joints was substantially reduced from $135m{\Omega}$ to $79m{\Omega}$ by increasing the flip chip bonding pressure from 85 MPa to 185 MPa. Improvement of the contact resistance characteristics at higher bonding pressure was attributed not only to the increased contact area between Cu chip bumps and Sn pads, but also to the severe plastic deformation of Sn pads caused during formation of the interlocking-joint structure. The parasitic capacitance increase due to the non-conductive adhesive locally surrounding the flip chip joints was estimated to be as small as 12.5%.