• Journal of Communications and Networks
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• v.1 no.3
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• pp.153-157
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• 1999

In this paper, we derive finite-dimensional non-linear fil-ters for optimally reconstructing speech signals in Switched Predic-tion vocoders, Code Excited Linear Prediction(CELP) and Differ-ential Pulse Code Modulation (DPCM). Our filter is an extension of the Hidden Markov filter.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.81-89
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• 1996

In this paper, a very efficient CAD algorithm is proposedd where rhodes formulae combined with distributed lowpass prototype filter in order to design the corrugated waveguide harmonic rejection filters accurately. The proposed algorithm resolves effectively the problem of proximity effect without any optimiation or iterative design process by using the internally convexed corrugated structure. A 13-section tapered corrugated lowpass filter has been designed by the proposed algorithm and fabricated. The experimental results are in good agreement with the calculated results.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06a
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• pp.957-962
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• 1994

Real-time RELP vocoder is implemented on the TMS320C25 DSP chip. The implemented system is IBM-PC add-on board and composed of analog in/out unit, DSP unit, memoy unit, IBM-PC interface unit and its supporting assembly software. Speech analyzer and synthesizer is implimented by DSP assembly software. Speech parameters such as LPC coefficients, base-band residuals, and signal gains is extracted by autocorrelation method and inverse filter and synthesized by spectral folding method and direct form synthesis filter in this board. And then, real-time RELP vocoder with 9.6Kbps is simulated by down-loading method in the DSP program RAM.

• ETRI Journal
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• v.36 no.1
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• pp.163-166
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• 2014

A microstrip dual-wideband bandpass filter using a multimode resonator (MMR) is proposed in this letter. The proposed MMR loaded with a T-shaped open-ended stub and a short-ended stub exhibits triple mode characteristics, and a synthesis method is developed to illustrate the wide passband with independently controllable center frequencies and bandwidths. To verify this design methodology, a dual-wideband filter with fractional bandwidths of 19.1% and 27.9% is designed and fabricated. The measured results agree with the simulations.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.11
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• pp.73-79
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• 1997

This paepr is concerned with the design of linear parameter varying filter that ensures H$^{2}$/$H^{\infty}$ performance for a class of linear parameter varying(LPV) plants. The state space matrices of plant are assumed to be dependent affinely on a vector of time varying parameter, and each parameter is assumed to be measured in real time. Using the linear matrix inequalities(LMIs), we can solve the synthesis problem and the solution of LMIs is carried out off-line. The designed filter is parameter varying and automatically scheduled along parameter trajectories. Because the solution of LMIs is carried out off-line, computation time of filter gain is reduced. The validity of the proposed algorithm is verifed through computer simulation..

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.43-46
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• 2011

A novel circuit structure of dual-band bandstop filters is proposed in this paper. This structure comprises two shunt-connected tri-section stepped impedance resonators with a transmission line in between. Theoretical analysis from the equivalent circuit and design procedures are described. We represented graphs for filter design from the derived synthesis equations by resonance condition of circuits. Notably, advantages of the proposed filter structure are compact size in design, wide range of realizable resonance frequency ratio, and more realizable impedances.

• Speech Sciences
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• v.8 no.4
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• pp.45-58
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• 2001

Modulated components of a speech signal are frequently used for speech coding, speech recognition, and speech synthesis. Time-frequency representation (TFR) reveals some information about instantaneous frequency, instantaneous bandwidth and boundary of each component of the considering speech signal. In many cases, the extraction of AM-FM components corresponding to instantaneous frequencies is difficult since the Fourier spectra of the components with time-varying instantaneous frequency are overlapped each other in Fourier frequency domain. In this paper, an efficient method decomposing speech signal into AM-FM components is proposed. A variable bandwidth filter is developed for the decomposition of speech signals with time-varying instantaneous frequencies. The variable bandwidth filter can extract AM-FM components of a speech signal whose TFRs are not overlapped in timefrequency domain. Also, amplitude and instantaneous frequency of the decomposed components are estimated by using Hilbert transform.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.68-71
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• 2003

An output multiplexer of manifold type is widely employed in a recent satellite transponder due to its small size and mass. For correct operation, channel fillers in manifold multiplexer must be singly terminated. In this paper, a simple synthesis method fur a single terminated filter is described. From the given method, a 4-pole singly terminated elliptic function filter for Ka band satellite transponder is designed. The filter is shown to be suitable for satellite application and its measured results agrees well with computed ones.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.22-27
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• 1997

This paper propose a novel VLSI architecture for a multiplierless FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a modulo unit. Since multipliers occupy large VLSI area, a multiplierless filter chip meeting real-time requirement can save large area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice faster and has smaller hardware than previous multiplierless filters. We developed VHDL models and performed logic synthesis using the 0.8.mu.m SOG (sea-of-gate) cell library. The chip has only 9,507 gates, was fabricated, and is running at 77MHz.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.188-191
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• 2000

This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.