• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.4
• /
• pp.275-280
• /
• 1999

The glass-to-glass electrostatic bonding process in vacuum environment was developed and the tubeless-packaged FED was fabricated based on the bonding process. The fabricated tubeless-packaged FED showed stable field emission characteristics and potential applicability to the FED tubeless packaging and vacuum in-line sealing.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.1530-1533
• /
• 2005

We investigated under-gate type carbon nanotube field emitter arrays (FEAs) for back light unit (BLU) in liquid crystal display (LCD). Gate oxide was formed by wet etching of ITO coated glass substrate instead of depositing $SiO_2$ on the glass substrate. Wet etching is easer and simpler than depositing and etching of thick gate oxide to isolate the gate metal from cathode electrode in triode. Field emission characteristic s of triode structure were measured. The maximum current density of 92.5 ${\mu}A/cm^2$ was when the gate and anode voltage was 95 and 2500 V, respectively at the anode-cathode spacing of 1500 ${\mu}m$.

• Proceedings of the KIEE Conference
• /
• 1995.07c
• /
• pp.1440-1441
• /
• 1995

We fabricated diode-type silicon field emitter array device and tested the current-voltage characteristics. Silicon oxide layer having the thickness of $1{\mu}m$ is grown in the (100) oriented n-type silicon substrates. Oxide layer is patterned by the mask with $10{\mu}m$ diameter circles. Silicon substrate is then etched using NAF 1 solution to form the sharp tip arrays as an electron source. In the UHV test station, we tested the current-voltage characteristics for the samples. Turn-on voltage was about 140V and maximum emission current was $310{\mu}A$ at 164V. We studied about silicon bonding process for future work, too.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.44 no.8
• /
• pp.8-15
• /
• 2007

In this paper, we fabricated the field emitter display using oxidized porous polysilicon(OPPS). Their field emission characteristics and the brightness were investigated for each pixel. The OPPS emitter was operated to each pixel using passive matrix for application of large panel display. We set up the proper thickness and width of upper electrode. The fine structure of OPPS was analyzed and the field emission characteristics of each pixel were investigated. As a result of field emission characteristics of different upper electrode thickness and width, we confirmed that the most efficient thickness was 2nm/7nm and increased the emission efficiency over the width of 2.5 mm. Even if field emission characteristics of each pixel was a little different but we confirmed the same leakage current and emission current, emission efficiency at each pixel. The leakage current and emission current was decreased according to the time increases but all of each pixel were uniformly decreased. We confirmed that the brightness of each pixel was not different and the brightness of OPPS field emitter was 700 cd/m2 at the Vps=20 V. Accordingly, the patterned OPPS field emitter can be applied to high quality field emission display devices.

• Journal of the Korean Vacuum Society
• /
• v.6 no.2
• /
• pp.103-108
• /
• 1997

Silicon field emitter arrays (FEAs) have been fabricated by a novel method employing a two-step tip etch and a spin-on-glass (SOG) etch-back process using double layered thermal/tetraethylortho-silicate (TEOS) oxides as a gate dielectric. A partial etching was performed by coating a low viscous photo resist and $O_2$ plasma ashing on order to form the double layered gate dielectric. A small gate aperture with low gate leakage current was obtained by the novel process. The hight and the end radius of the fabricated emitter was about 1.1 $\mu\textrm{m}$ and less than 100$\AA$, respectively. The anode emission current from a 256 tips array was turned-on at a gate voltage of 40 V. Also, the gate current was less than 0.1% of the anode current.

• Journal of Korean Vacuum Science & Technology
• /
• v.3 no.1
• /
• pp.33-37
• /
• 1999

We present, for the first time, a prototype active-matrix field emission display (AMFED) with 25$\times$25 pixels in which polycrystalline silicon fie이 emitter array (poly-Si FEA) and thin-film transistor (TFT) were monolityically intergrated on an insulating substrate. The FEAs showed relatively large electron emissions above at a gate voltage of 50 V, and the TFTs were designed to have low off-stage currents even though at high drain voltages. The intergrated poly-Si TFT controlled electron emissions of the poly-Si FEA actively, resulting in improvement in the emission stability and reliability along with a low-voltage control of field emission below 25V. With the prototype AMFED we have displayed character patterns by low-boltage pertipheral circuits of 15 V in a high vacuum chamber.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.11 no.7
• /
• pp.508-516
• /
• 1998

Mo-tip field emitter arrays(FEAs) were fabricated by conventional Spindt process and their life time characteristics and failure mode were evaluated. The fabricated Mo-tip FEA could generate at least $0.35\{mu} A/tip$ emission current for about 320 persistently under a constant gate bias of 140 V and was finally destroyed through self-healing mode. Thin diamond-like carbon films were coated on the M-tip by plasma-enhanced CVD and the dependence of emission properties upon the DLC thickness was investigated. By DLC coating, the turn-on voltage and emission current were appeared to be improved whereas the current fluctuation was increased in the DLC thickness range of $0~1,000\{AA}$.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.48 no.9
• /
• pp.662-664
• /
• 1999

We fabricated AC-TFEL device having cone-shaped Si micro-tip reflector array based on the process which have been conventionally employed for the Si-tip field emitter array in FED system. As a result, the AC-TFEL device having a new geometrical structure could generate well concentrated visible white-light from 3600 reflectors/pixel under bipolar pulse excitation mode only by edge-emission mechanism.

• Proceedings of the Korean Vacuum Society Conference
• /
• 1997.02a
• /
• pp.213-214
• /
• 1997

• Journal of the Korean Vacuum Society
• /
• v.7 no.2
• /
• pp.88-93
• /
• 1998

The fabrication process and emission characteristics of gated silicon field emitter arrays(FEAs) using chemical-mechanical-polishing (CMP) method are described. Novel fabrication techniques consisting of two-step dry etching with oxidation of silicon and CMP processes were developed for the formation of sharp tips and clear-cut edged gate electrodes, respectively. The gate height and aperture could be easily controlled by varying the polishing time and pressure in the CMP process. We obtained silicon FEAs having self-aligned and clear-cut edged gate electrode opening by eliminating the dishing problem during the CMP process with an oxide mask layer. The tip height of the finally fabricated FEAs was about 1.1 $\mu$m and the end radius of the tips was smaller than 100 $\AA$. The emission current meaured from the fabricated 2809 tips array was about 31 $\mu$A at a gate voltage of 80 V.