• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.737-743
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• 2008

I compare my parameter estimation methodoloay with existing method, considering both of testing effort and fault detecting rate simultaneously in software reliability modeling. Generally speaking, fault detection/removal mechanism depends on how apply previous fault detection/removal and testing effort of S/W. The fault removal efficiency makes large influence to the reliability growth, testing and removal cost in developing stage S/W. This is very useful measure during all the developing stages and much helpful for the developer to estimate debugging efficiency, and furthermore, to anticipate additional working amount.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.1-9
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• 1994

This paper analyzes the faults and their mechanism of CMOS ICs using IDDQ testing technique and evalutes the reliability of the chips that fail this test. It is implemented by the three testing phases, initial test, burn-in and life test. Each testing phase includes the parametric test, functional test, IDDQ test and propagation delay test. It is shown that the short faults such as gate-oxide short, bridging can be only detected by IDDQ testing technique and the number of test patterns for this test technique is very few. After first burn-in, the IDDQ of some test chips is decreased, which is increased in conventional studies and in subsequent burn-in, the IDDQ of all test chips is stabilized. It is verified that the resistive short faults exist in the test chips and it is deteriorated with time and causes the logic fault. Also, the new testing technique which can easily detect the rsistive short fault is proposed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.266-276
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• 2001

Due to the rapid development of semiconductor technology, the complexity of VLSI circuits has heavily increased. With the increased densities of integrated circuits, several different types of faults can occur Thus, testing such circuits is becoming a sever problem. Delay testing can detect system timing failures caused by delay faults. However, the conventional delay fault coverage in terms of the number of detected faults may not be an effective measure of delay testing because, unlike a stuck-at-faults, the impact of a delay fault is dependent on its delay defect size rather than on its existence. Thus, the effectiveness of delay testing is dependent on the propagation delay of the path to be tested, the delay defect size, and the system clock interval. This paper proposes a new delay defect fault coverage that considers both propagation delay of the path to be tested and additional delay defect size. And the relationship between delay defect fault coverage and defect level is analyzed.

• Proceedings of the KIEE Conference
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• 2003.11a
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• pp.79-81
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• 2003

This paper presents development and testing of a new numerical spectral domain algorithm devoted to blocking unsuccessful automatic reclosing onto permanent faults and the fault distance calculation. The arc voltage amplitude and the fault distance are calculated from the fundamental and third harmonics of the terminal voltages and currents phasors. From the calculated arc voltage amplitude it can be concluded if the fault is transient arcing fault or permanent arcless fault. If the fault is permanent automatic reclosure should be blocked. The algorithm can be applied for adaptive autoreclosure, distance protection, and fault location. The results of algorithm testing through computer simulation are given.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.3
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• pp.932-951
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• 2021

The effectiveness of testing in Model-based Testing (MBT) for Software Product Line (SPL) can be achieved by considering fault detection in test case. The lack of fault consideration caused test case in test suite to be listed randomly. Test Case Prioritization (TCP) is one of regression techniques that is adaptively capable to detect faults as early as possible by reordering test cases based on fault detection rate. However, there is a lack of studies that measured faults in MBT for SPL. This paper proposes a Test Case Prioritization (TCP) approach based on dissimilarity and string based distance called Last Minimal for Local Maximal Distance (LM-LMD) with Dice-Jaro-Winkler Dissimilarity. LM-LMD with Dice-Jaro-Winkler Dissimilarity adopts Local Maximum Distance as the prioritization algorithm and Dice-Jaro-Winkler similarity measure to evaluate distance among test cases. This work is based on the test case generated from statechart in Software Product Line (SPL) domain context. Our results are promising as LM-LMD with Dice-Jaro-Winkler Dissimilarity outperformed the original Local Maximum Distance, Global Maximum Distance and Enhanced All-yes Configuration algorithm in terms of Average Fault Detection Rate (APFD) and average prioritization time.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.881-885
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• 2018

In order to develop a gas circuit breaker (GCB), the breaking performance of the short line fault (SLF) should be prioritized over that of the breaker terminal fault (BTF). In brief, it is necessary to evaluate the thermal characteristics of the insulating gas that is filled in a GCB. In the process of developing a GCB, many companies use the simplified synthetic testing facility (SSTF).In order to evaluate the SLF breaking performance of a GCB with a long minimum arcing time, a modifications to the conventional SSTF was proposed. In this study, we developed the SSTF with a modified transient recovery voltage circuit. The performance of the newly developed SSTF was verified by an $L_{90}$ breaking performance test on a rating combination of 170 kV, 50 kA, and 60 Hz.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.2
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• pp.173-183
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• 1996

In this paper, a new structure that can do fault detection and location of digial logic circuits more efficiently using current testing techniques is proposed. In the conventional method, observation point for steady state power supply current was only one, but in the proposed method more fault classes are divided for fault detection and location through the ovservation of steady state power supply current at two points. Also, it is shown that this structure can be easily applied in detection of stuck-open fault which is not easy to do testing with conventional current testing techniques. In the presented mehtod, an extra trasnistor is used, and current path is made compulsorily in the CMOS circuits in which no current path can be established in steady state, then it can be known that stuck-open tault is in the MOS transistor on the considering current path, if this path disappears due to stuck-open fault. The validity and the effectiveness is shwon, thorugh the SPICE simulation of circuits with fault and the current path search experiment using current path search program based on transistor short model wirtten in C language on SUN sparc workstation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.10A
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• pp.1205-1214
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• 2004

For tile physical defects occurring in CMOS circuits which are not handled well by voltage-based testing, current testing is remarkable testing technique. Fault models based on defects must accurately describe the behaviour of the circuit containing the defect. In this paper, An efficient collapsing algorithm for fault models often used in current testing is proposed. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults that have to be considered by fault collapsing and its usefulness in various current based testing models.

• Journal of KIISE
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• v.43 no.9
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• pp.998-1007
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• 2016

In recent years, the cost of automotive ECU (Electronic Control Unit) has accounted for more than 30% of total car production cost. However, the complexity of testing and debugging an automotive ECU is increasing because automobile manufacturers outsource automotive ECU production. Therefore, a large amount of cost and time are spent to localize faults during testing an automotive ECU. In order to solve these problems, we propose a fault localization method in memory for developers who run the integration testing of automotive ECU. In this method, memory is partitioned by utilizing memory map, and fault-suspiciousness for each partition is calculated by utilizing memory update information. Then, the fault-suspicious region for partitions is decided based on calculated fault-suspiciousness. The preliminary result indicated that the proposed method reduced the fault-suspicious region to 15.01(%) of memory size.

• Proceedings of the KIEE Conference
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• 2005.07a
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• pp.700-702
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• 2005

The most electrical apparatus should be able to withstand short-time current and peak current during a specified short time until circuit breakers have interrupted fault current. It defines the short-time withstand ability of electric a apparatus to be remain for a time interval under high fault current conditions. It is specified by both dynamic ability and thermal capability. KERI(Korea Electrotechlology Research Institute) recently constructed the new short-time current and low voltage short circuit testing facilities. This paper shows short- circuit calculation of transformer and describes high current measuring system, and evaluate the result of short-time withstand test used in $3{\phi}$ 90MVA short-time current testing facilities.