The Journal of Korean Institute of Communications and Information Sciences (한국통신학회논문지)

The Korean Institute of Commucations and Information Sciences (한국통신학회)
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An Efficient Collapsing Algorithm for Current-based Testing Models in CMOS VLSI

CMOS VLSI를 위한 전류 테스팅 기반 고장모델의 효율적인 중첩 알고리즘

  • 김대익 (여수대학교 자연과학대학 반도체학과) ;
  • 배성환 (한려대학교 멀티미디어정보통신공학과)
  • Published : 2004.10.01
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Abstract

For tile physical defects occurring in CMOS circuits which are not handled well by voltage-based testing, current testing is remarkable testing technique. Fault models based on defects must accurately describe the behaviour of the circuit containing the defect. In this paper, An efficient collapsing algorithm for fault models often used in current testing is proposed. Experimental results for ISCAS benchmark circuits show the effectiveness of the proposed method in reducing the number of faults that have to be considered by fault collapsing and its usefulness in various current based testing models.

CMOS 회로에서 발생하는 물리적인 결함에 대해서 전류 테스팅은 전압 테스팅으로 검출할 수 없는 많은 결함을 효율적으로 검출할 수 있는 기법이다. 테스트 회로에 존재하는 결함이나 장애의 영향을 기술하기 위해서 사용되는 고장모델은 실제적인 장애를 정확하게 모델링해야 한다. 본 논문에서는 전류 테스팅에 자주 이용되는 고장모델을 위한 효율적인 중첩 알고리즘을 제안한다. ISCAS 벤치마크 회로의 모의실험을 통하여 제안된 방식이 고려되는 고장의 수를 효과적으로 감소시킬 수 있고 다양한 전류 테스팅 방식의 고장모델에 더 적합함을 확인하였다.

Keywords

References

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