• Title/Summary/Keyword: Fault Propagation

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Implementation of ATPG for IdDQ testing in CMOS VLSI (CMOS VLSI의 IDDQ 테스팅을 위한 ATPG 구현)

  • 김강철;류진수;한석붕
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.3
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    • pp.176-186
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    • 1996
  • As the density of VLSI increases, the conventional logic testing is not sufficient to completely detect the new faults generated in design and fabrication processing. Recently, IDDQ testing becomes very attractive since it can overcome the limitations of logic testing. In this paper, G-ATPG (gyeongsang automatic test pattern genrator) is designed which is able to be adapted to IDDQ testing for combinational CMOS VLSI. In G-ATPG, stuck-at, transistor stuck-on, GOS (gate oxide short)or bridging faults which can occur within priitive gate or XOR is modelled to primitive fault patterns and the concept of a fault-sensitizing gate is used to simulate only gates that need to sensitize the faulty gate because IDDQ test does not require the process of fault propagation. Primitive fault patterns are graded to reduce CPU time for the gates in a circuit whenever a test pattern is generated. the simulation results in bench mark circuits show that CPU time and fault coverage are enhanced more than the conventional ATPG using IDDQ test.

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Important Parameters Related With Fault for Site Investigation of HLW Geological Disposal

  • Jin, Kwangmin;Kihm, You Hong;Seo, Dong-Ik;Kim, Young-Seog
    • Journal of Nuclear Fuel Cycle and Waste Technology(JNFCWT)
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    • v.19 no.4
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    • pp.533-546
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    • 2021
  • Large earthquakes with (MW > ~ 6) result in ground shaking, surface ruptures, and permanent deformation with displacement. The earthquakes would damage important facilities and infrastructure such as large industrial establishments, nuclear power plants, and waste disposal sites. In particular, earthquake ruptures associated with large earthquakes can affect geological and engineered barriers such as deep geological repositories that are used for storing hazardous radioactive wastes. Earthquake-driven faults and surface ruptures exhibit various fault zone structural characteristics such as direction of earthquake propagation and rupture and asymmetric displacement patterns. Therefore, estimating the respect distances and hazardous areas has been challenging. We propose that considering multiple parameters, such as fault types, distribution, scale, activity, linkage patterns, damage zones, and respect distances, enable accurate identification of the sites for deep geological repositories and important facilities. This information would enable earthquake hazard assessment and lower earthquake-resulted hazards in potential earthquake-prone areas.

Correction of the delay faults of command reception in satellite command processor (위성용 명령 처리기의 명령 입수 지연 오류 정정)

  • Koo, Cheol-Hea;Choi, Jae-Dong
    • Proceedings of the KIEE Conference
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    • 2005.05a
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    • pp.194-196
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    • 2005
  • The command processor in satellite handles the capability of the process of command transmitted from ground station and deliver the processed data to on board computer in satellite. The command processor is consisted of redundant box to increase the reliability and availability of the capability. At each command processor, the processing time of each command processor is different, so the mismatch of processing time makes it difficult to timely synchronize the reception to on board computer and even will be became worse under the command processor's fault. To minimize the tine loss induced by the command processor's fault on board computer must analyze the time distribution of command propagation. This paper presents the logic of minimizing the delay error of command propagation the logic of analyzing the output of command processor.

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An efficient test pattern generation based on the fast redundancy identification (빠른 무해 인식에 의한 효율적인 테스트 패턴 생성)

  • 조상윤;강성호
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.8
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    • pp.39-48
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    • 1997
  • The fast redundancy identification is required to perform an efficient test pattern genration. Due to the reconvergent fanouts which make the dependency among objectives and the fault propagation blocking, there may exist redundnat faults in the cirucit. This paper presents the isomorphism identification and the pseudo dominator algorithms which are useful to identify redundant faults in combinational circuits. The isomorphism identification algorithm determines whether mandatory objectives required for fault detection cannot be simultaneously satisfied from primary input assignments or not using binary decision diagrma. The pseudo dominator algorithm determines whether faults propagation is possible or not by considering all paths at a given fanout node. Several experiments using ISCAS 85 benchmark circuits demonstrate the efficiency and practicability of the algorithms.

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Optical Wireless Access Point Agent Networks

  • Lee, Tae-Gyu
    • Journal of the Optical Society of Korea
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    • v.13 no.1
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    • pp.98-106
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    • 2009
  • This paper proposes an optical wireless transfer agent method which realizes the continuous and swift data transfer of optical wireless terminals in optical wireless networks. The unguided wireless channel generally shows frequent link disconnections and propagation delays due to weak wireless links. Specially speaking, optical wireless channels have more vulnerable links and roaming propagation delays relative to the weakness of the previous RF channels due to their low signal connectivity and small geographic coverage. Conventional optical wireless network protocols did not consider any fault models about physical link faults. Consequently, they have shown data transfer inefficiency for both data link control and physical wireless link control. To overcome these optical wireless environmental problems, this paper suggests a new wireless access point (or base station) agent system, which provides wireless or mobile clients with previous link layer protocols compensated.

Characteristics of a superconductive fuse according to applied voltages (초전도 퓨즈의 전압별 특성)

  • Choi, Hyo-Sang
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2004.05b
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    • pp.169-172
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    • 2004
  • We present the basic properties of a superconducting current limiting fuse (SCLF) based on YBCO/Au films. The SCLFs consists of YBCO stripes covered with Au layers for current shunt. Under the source voltage of 100 $V_{rms}$, the longer the duration time of fault current was, the shorter its discharge time was. The duration time of fault current and its discharge time were reduced by increased voltages in the range of 200 - 300 $V_{rms}$. We thought that this was because the quench propagation was limited by local melting generated with higher voltage.

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Estimation of Wave Parameters for Probabilistic Tsunami Hazard Analysis Considering the Fault Sources in the Western Part of Japan (일본 서부 단층 지진원을 고려한 확률론적 지진해일 재해도 분석의 파고 변수 도출)

  • Rhee, Hyun-Me;Kim, Min Kyu;Sheen, Dong-Hoon;Choi, In-Kil
    • Journal of the Earthquake Engineering Society of Korea
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    • v.18 no.3
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    • pp.151-160
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    • 2014
  • Probabilistic tsunami hazard analysis (PTHA) is based on the approach of probabilistic seismic hazard analysis (PSHA) which is performed using various seismotectonic models and ground-motion prediction equations. The major difference between PTHA and PSHA is that PTHA requires the wave parameters of tsunami. The wave parameters can be estimated from tsunami propagation analysis. Therefore, a tsunami simulation analysis was conducted for the purpose of evaluating the wave parameters required for the PTHA of Uljin nuclear power plant (NPP) site. The tsunamigenic fault sources in the western part of Japan were chosen for the analysis. The wave heights for 80 rupture scenarios were numerically simulated. The synthetic tsunami waveforms were obtained around the Uljin NPP site. The results show that the wave heights are closely related with the location of the fault sources and the associated potential earthquake magnitudes. These wave parameters can be used as input data for the future PTHA study of the Uljin NPP site.

Parameter identifiability of Boolean networks with application to fault diagnosis of nuclear plants

  • Dong, Zhe;Pan, Yifei;Huang, Xiaojin
    • Nuclear Engineering and Technology
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    • v.50 no.4
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    • pp.599-605
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    • 2018
  • Fault diagnosis depends critically on the selection of sensors monitoring crucial process variables. Boolean network (BN) is composed of nodes and directed edges, where the node state is quantized to the Boolean values of True or False and is determined by the logical functions of the network parameters and the states of other nodes with edges directed to this node. Since BN can describe the fault propagation in a sensor network, it can be applied to propose sensor selection strategy for fault diagnosis. In this article, a sufficient condition for parameter identifiability of BN is first proposed, based on which the sufficient condition for fault identifiability of a sensor network is given. Then, the fault identifiability condition induces a sensor selection strategy for sensor selection. Finally, the theoretical result is applied to the fault diagnosis-oriented sensor selection for a nuclear heating reactor plant, and both the numerical computation and simulation results verify the feasibility of the newly built BN-based sensor selection strategy.

An Efficient Parallel Evaluation Algorithm for Fast Fault Simulation (고속 고장 시뮬레이션을 위한 효율적인 병렬 평가 알고리듬)

  • Min Sup Kang
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.31A no.6
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    • pp.169-176
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    • 1994
  • This paper describes an efficient parallel evaluation algorithm for accelerating fault simulation, which can be applied to combinational circuits. The method is based on a combination of all the advantages in parallel, deductive and concurrent schemes in terms of evaluation and propagation of fautly gates for achieving high performance and handling multi-valued signal. We also propose a new fault grouping procedure to increase parallel operation of fault bits by packing active faults which occur in the same signal line densely into the same fault group. The algorithm has been implemented in C language on a Sun 3/260, and experimental results for ISCAS'85 benchmark circuits have been shown that this algorithm is 2.6 to 8.2 times faster than the conventional cocurrent fault simulation algorithm.

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A Study on the fault Detection using output Sequence in Combinational Logic Networks (출력순자를 이용한 조합회로의 고장검출에 관한 연구)

  • Han, Hee;Park, Kue-Tae
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.17 no.4
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    • pp.31-37
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    • 1980
  • In this paper, we are concerned with the problems of fault- detection for combinational logic networks. The method which we can obtain the complete test sets using propagation of primitive test sets is presented by considering the relation between test sets of each line. A new method is proposed that can detect the fault through the observation of the output variance by applying only the test sets equivalent to the number of inputs We found that the method is much improved compared to the conventional fault detecting procedure that requires applying the complete test sets to the logic networks.

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