• Journal of KIISE:Information Networking
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• v.28 no.3
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• pp.355-368
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• 2001

Protocol conformance test is used to promote interoperability of protocol implementatons developed by venders. Non-interopcrability between protocol implementations may be caused by ambiguity and/or misintellJretation of the protocol specifications by vendors. Conventional method on protocol conformance test has been standardized by IS0;IEC JTCI with the purpose of whether a protocol implementation conforms to its specification. However, sometimes the conventional method gives wrong test results because the test is based on static test sequences. This problem is caused by the fact as some failed transitions of a protocol FSM included in test sequences have an effect on the test result of transitions to be tested. In this paper, a new approach called Dynamic Conformance Test Method (DCTM) is proposed to solve this problem. DCTM dynamically selects test sequence durng testing depending on an information showing an alternative path without failed tranistions. As a result, the fault coverage of the DCTM is better than that of the conventional test method. In order to demonstrate the fault coverage of DCTM compared to that of the conventional method. a testing tool is implemented and appied to the TCP protocol.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.640-648
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• 2014

Excessive power dissipation is one of the major issues in the testing of VLSI systems. Many techniques are proposed for scan test, but there are not so many for logic BIST because of its unmanageable randomness. This paper presents a novel low switching activity BIST scheme that reduces toggle frequency in the majority of scan chain inputs while allowing a small portion of scan chains to receive pseudorandom test data. Reducing toggle frequency in the scan chain inputs can reduce test power but may result in fault coverage loss. Allowing a small portion of scan chains to receive pseudorandom test data can make better uniform distribution of 0 and 1 and improve test effectiveness significantly. When compared with existing methods, experimental results on larger benchmark circuits of ISCAS'89 show that the proposed strategy can not only reduce significantly switching activity in circuits under test but also achieve high fault coverage.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.2
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• pp.93-101
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• 2003

Scan design is a structured design-for-testability technique in which flip-flops are re-designed so that the flip-flops are chained in shift registers. The scan design cannot be used in a design with scan design rule violations without modifying the design. The most important scan design rule is concerning clock and reset signals to pins of the flip-flops or scan cells. Clock and Reset pins of every scan cell must be controllable from top-level ports. We propose a new technique to re-design gated clocks and resets which violate the scan design rule concerning the clock and reset pins. This technique substitutes synchronous sequential circuits for gated clock and reset designs, which removes the clock and reset rule violations and improves fault coverage of the design. The fault coverage is improved from $90.48\%$ to $100.00\%$, from $92.31\%$ to $100.00\%$, from $95.45\%$ to $100.00\%$, from $97.50\%$ to $100.00\%$ in a design with gated clocks and resets.

• The KIPS Transactions:PartD
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• v.11D no.6
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• pp.1287-1294
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• 2004

Recently relationships between reliability measures and the coverage have been developed for evaluation of software reliability. Particularly the mean value function of the coverage-based software reliability growth model is important because of its key role in rep-resenting the software reliability growth. In this paper, we first review the problems of the existing mean value functions with respect to the assumptions on which they are based. Then a new mean value function is proposed. The new mean value function is developed for a general testing environment in which imperfect fault detection and repeated construct execution are allowed. Finally performance of the proposed model is empirically evaluated by applying it to a real data set.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.1948-1957
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• 1996

The conformance testing of communication protocol is the process to evaluate whether the protocol implemented is identified with standard specification. By evaluating how generated test cases detect many faults, it can be used with standard estimating efficiency of conformance testing. The method that evaluates the capability of fault coverage for test cases, has been researched by mathematical analysis and simulation. In this paper, we pointed out the problem of existing method and proposed new evaluation model of fault covergage for test case which generated by foult model. Also, we analyzed the results comparing to the existing evaluation method and proved its validity.

• Nuclear Engineering and Technology
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• v.33 no.6
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• pp.596-604
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• 2001

This paper quantitatively presents the effects of important factors of the probabilistic safety assessment (PSA) of safety-critical digital systems. The result which is quantified using fault tree analysis methodology shows that these factors remarkably affect the system safety. In this paper we list the factors which should be represented by the model for PSA. Based on the PSA experience, we select three important factors which are expected to dominate the system unavailability. They are the avoidance of common cause failure, the coverage of fault tolerant mechanisms and software failure probability. We Quantitatively demonstrate the effect of these three factors. The broader usage of digital equipment in nuclear power plants gives rise to the safety problems. Even though conventional PSA methods are immature for applying to microprocessor-based digital systems, practical needs force us to apply it because the result of PSA plays an important role in proving the safety of a designed system. We expect the analysis result to provide valuable feedback to the designers of digital safety- critical systems.

• The Journal of Information Technology
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• v.10 no.2
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• pp.47-64
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• 2007

Finite failure NHPP models presented in the literature exhibit either constant, monotonic increasing or monotonic decreasing failure occurrence rates per fault. Accurate predictions of software release times, and estimation of the reliability and availability of a software product require quantification of a critical element of the software testing process : test coverage. This model called enhanced non-homogeneous poission process(ENHPP). In this paper, exponential coverage and S-coverage model was reviewed, proposes the exponentiated exponential coverage reliability model, which maked out efficiency substituted for gamma and Weibull model(2 parameter shape illustrated by Gupta and Kundu(2001). In this analysis of software failure data, algorithm to estimate the parameters used to maximum likelihood estimator and bisection method, model selection based on SSE statistics for the sake of efficient model, was employed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• The Transactions of the Korea Information Processing Society
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• v.5 no.9
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• pp.2378-2387
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• 1998

This thesis proposes a design algorithm of an efficient space response compactor for Built-In Self-Testing of VLSI circuits. The proposed design algorithm of space compactors can be applied independently from the structure of Circuit Cnder Test. There are high hardware overhead cost in conventional space response compactors and the fault coverage is reduced by aliasing which maps faulty circuit's response to fault-free one. However, the proposed method designs space response compactors with reduced hardware overheads and does not reduce the fault coverage comparing to conventional method. Also, the proposed method can be extended to general N -input logic gate and design the most efficient space response L'Ompactors according to the characteristies of output sequence from CUT. The prolxlsed design algorithm is implemented by C language on a SUN SPARC Workstation, and some experiment results of the simulation applied to ISCAS'85 benchmark circuits with pseudo random patterns generated bv LFSR( Linear Feedback Shift Register) show the efficiency and validity of the proposed design algorithm.

• The Transactions of the Korea Information Processing Society
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• v.7 no.10
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• pp.3226-3235
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• 2000

The more complex and larger semiconductor integraed circuits become, the core important delay test becomes which guarantees that semiconductor integrated circuits operate in time. In this paper, we propose a new partial enhanced scan method that can generate test patterns for path delay faults offectively. We implemented a new partial enhanced scan method based on an automatic test pattern generator(ATPG) which uses implication and justification . First. we generate test patterns in the standard scan environment. And if test patterns are not generated regularly in the scan chain, we determine flip-flops which applied enhanced scan flip-flops using the information derived for running an automatic test pattern generator inthe circuti. Determming enhanced scan flip-flops are based on a fault coverage or a hardware overhead. through the expenment for JSCAS 89 benchmark sequential circuits, we compared the fault coverage in the standard scan enviroment and enhance scan environment, partial enhanced scan environment. And we proved the effectiveness of the new partial enhanced scan method by identifying a high fault coverage.