• 제목/요약/키워드: Fast-Time Simulation

검색결과 977건 처리시간 0.03초

REGENERATIVE BOOTSTRAP FOR SIMULATION OUTPUT ANALYSIS

  • Kim, Yun-Bae
    • 한국시뮬레이션학회:학술대회논문집
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    • 한국시뮬레이션학회 2001년도 춘계 학술대회 논문집
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    • pp.169-169
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    • 2001
  • With the aid of fast computing power, resampling techniques are being introduced for simulation output analysis (SOA). Autocorrelation among the output from discrete-event simulation prohibit the direct application of resampling schemes (Threshold bootstrap, Binary bootstrap, Stationary bootstrap, etc) extend its usage to time-series data such as simulation output. We present a new method for inference from a regenerative process, regenerative bootstrap, that equals or exceeds the performance of classical regenerative method and approximation regeneration techniques. Regenerative bootstrap saves computation time and overcomes the problem of scarce regeneration cycles. Computational results are provided using M/M/1 model.

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ATO 자동운전 기반의 무인운전 경전철 TPS에 관한 연구 (A Study on TPS based on ATO for Driverless LRT)

  • 이창형;이종우
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 2008년도 추계학술대회 논문집
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    • pp.1132-1137
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    • 2008
  • Automatic Operation based on ATO (Automatic Train Operation) is necessary for driverless Light Rail Transit business. When this kind of driverless LRT operation plan is made, TPS (Train Performance Simulation) is traditionally simulated at all-out mode and coasting mode based on manual operation. Commercial schedule speed equals to all-out speed minus $9{\sim}15%$ make-up margin. Coasting mode TPS simulation is also run at commercial schedule speed to calculate run time and energy consumption. But TPS based on manual operation should make an improvement on accuracy in case of driverless LRT operation Plan. In this paper, new fast mode TPS simulation using ATO pattern is proposed and show near actual ATO result. The actual ATO pattern can be accurately simulated with the introduction of 4 parameters such as commercial braking rate, jerk, station stop profile and grade converted distance. Normal mode TPS simulation for commercial schedule speed can be designed to have fast mode trip time plus 3 seconds/km margin recommended by korean standard LRT specification.

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샘플링 시간에 대해 개선된 Singular Perturbation 기반 STT missile 디지털 autopilot 설계 (Design of an improved STT missile digital autopilot with respect to sampling time)

  • 정선태
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 1997년도 한국자동제어학술회의논문집; 한국전력공사 서울연수원; 17-18 Oct. 1997
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    • pp.468-471
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    • 1997
  • In this paper, we investigate the time-sampling effects on the digital implementation of singular perturbation based STT autopilot with excellent performance and propose a compensation method for the time-sampling effects. In digitization of analog STT autopilot, it is found that the stability margin of the fast dynamics is mostly affected to lead to rapid decrease. Under the this analysis, a composite digital controller with additional compensator for fast dynamics is proposed to improve the time-sampling effect and a simulation verifies the result.

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서포트 추정을 이용한 빠른 이미지 사영 기반 타원형 물체 복원 기법 (Fast Elliptic Object Reconstruction from Projections by Support Estimation)

  • 고경준;이정우
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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    • pp.105-106
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    • 2007
  • We present a fast reconstruction technique for elliptic objects, which can be applied to real-time computer tomography (CT) for simple geometric objects. It will be also shown that only 3 projections are needed to reconstruct an ellipse. A piecewise quadratic model is also proposed for more efficient Kalman filter based support estimation, which is used for the fast reconstruction technique. The performance of the piecewise quadratic model is compared with that of the existing piecewise linear model. Simulation results for the fast reconstruction are also presented.

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컴파일방식 시뮬레이션 기법을 이용한 ASIP 어셈블리 시뮬레이터의 성능 향상 (Performance Improvement of ASIP Assembly Simulator Using Compiled Simulation Technique)

  • 김호영;김탁곤
    • 한국시뮬레이션학회논문지
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    • 제12권2호
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    • pp.45-53
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    • 2003
  • This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.

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계층 전이가 가능한 다계층 대기행렬의 빠른 시뮬레이션 (Fast Simulation of Overflow Probabilities in Multi-Class Queues with Class-Transition)

  • 송미정;배경순;이지연
    • Communications for Statistical Applications and Methods
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    • 제16권2호
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    • pp.217-228
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    • 2009
  • 계층 전이가 가능한 다계층 대기행렬에 대한 빠른 시뮬레이션 방법을 제시하고 이를 이용하여 총 고객의 수가 적정 수준을 초과하는 과부하 발생 확률과 과부하 발생시 각 계층별 평균 고객의 수를 추정한다. 또한 이들 값들이 시스템의 총 로드나 계층별 로드에 따라 어떤 차이를 보이는지도 빠른 시뮬레이션을 통해 서로 비교한다.

구형파를 이용한 전극계면 분석용 고속 임피던스 분석기의 설계변수 확정을 위한 컴퓨터 시뮬레이션 (Computer simulation to determine system parameters of the square-wave adapted fast impedance analyzer for the electrode - electrolyte interface analysis)

  • 김기련;김광년;심윤보;전계록;정동근
    • 한국시뮬레이션학회논문지
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    • 제14권2호
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    • pp.45-55
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    • 2005
  • There are electric double layer capacitance, polarization resistance and solution resistance in the interface between electrode and solution. Electrode process could be evaluated by the electrical impedance analysis. The necessities of the electrochemical cell analysis with high speed impedance analyzer are followings: minimization of the effects of electric stimulation on electrochemical cell and the concentration of reactive materials, and optimization of impedance signal resolution. This paper represents the design criteria for the selection and stimulation to develop fast impedance analyzer prototype for a electrochemical cell. It was suggested that the design of 470k sample/s sampling rate, 13 bit ABC resolution, and 140ms recording time is required for high speed impedance analysis system in frequency range between dc and 10kHz.

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CEFR control rod drop transient simulation using RAST-F code system

  • Tuan Quoc Tran;Xingkai Huo;Emil Fridman;Deokjung Lee
    • Nuclear Engineering and Technology
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    • 제55권12호
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    • pp.4491-4503
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    • 2023
  • This study aimed to verify and validate the transient simulation capability of the hybrid code system RAST-F for fast reactor analysis. For this purpose, control rod (CR) drop experiments involving eight separate CRs and six CR groups in the China Experimental Fast Reactor (CEFR) start-up tests were utilized to simulate the CR drop transient. The RAST-F numerical solution, including the neutron population, time-dependent reactivity, and CR worth, was compared against the measurement values obtained from two out-of-core detectors. Moreover, the time-dependent reactivity and CR worth from RAST-F were verified against the results obtained by the Monte Carlo code Serpent using continuous energy nuclear data. A code-to-code comparison between Serpent and RAST-F showed good agreement in terms of time-dependent reactivity and CR worth. The discrepancy was less than 160 pcm for reactivity and less than 110 pcm for CR worth. RAST-F solution was almost identical to the measurement data in terms of neutron population and reactivity. All the calculated CR worth results agreed with experimental results within two standard deviations of experimental uncertainty for all CRs and CR groups. This work demonstrates that the RAST-F code system can be a potential tool for analyzing time-dependent phenomena in fast reactors.

SSMS에서 동적 공구할당을 고려한 부품투입 알고리즘의 시뮬레이션 분석 (Simulation Analysis of Part Release Algorithm under Dynamic Tool Allocation in SSMS)

  • 이충수
    • 한국시뮬레이션학회논문지
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    • 제8권1호
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    • pp.63-76
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    • 1999
  • Recently in manufacturing environment, manufacturing order is characterized by unstable market demand, shorter product life cycle, a variety of product and shorter production lead time. In order to adapt this manufacturing order, flexible manufacturing systems(FMS) in manufacturing technology advances into the direction that machines become further versatile functionally and that tools are controlled by fast tool delivery device. Unlike conventional FMS to mainly focus on part flow, it is important to control tool flow in single-stage multimachine systems(SSMS), consisting of versatile machines and fast tool delivery device. This research is motivated by the thought that exact estimation of tool competition at part release in SSMS enhances the system performance. In this paper, in SSMS under dynamic tool allocation strategy to share tools among machines, we propose real-time part release and tool allocation algorithms which can apply real factory and which can improve system performance.

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시뮬레이션 기반의 지상지연 프로그램 적용방안에 관한 연구 - 제주국제공항을 사례로 - (A Study on Simulation-based Method for Implementation of Ground Delay Program for Jeju International Airport)

  • 이영종;조지은;백호종
    • 한국항공운항학회지
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    • 제23권1호
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    • pp.41-48
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    • 2015
  • Being a cost-efficient solution for alleviating the traffic congestion in airspace, Air Traffic Flow Management (ATFM) has drawn more attentions from not only air traffic controllers but also researchers in the field of Air Traffic Management (ATM). Among other ATFM initiatives, it is believed that Ground Delay Program (GDP) could be effectively applied to reduce the congestion particularly in the relatively small airspace with dense traffic demand. This paper introduces a novel way that suggests flights to be delayed on the departing airports together with amount of the delays (in time) for those flights to be delayed. Adopting a fast-time simulation for predicting airspace delay of each flight for a given flight plan, the method is designed to iteratively and incrementally adjust the departure times in the plan towards reducing total airspace delays. Applying the method to Jeju airport with a hypothetically high demand, the paper demonstrates the airspace delay could be significantly reduced by applying GDP at Gimpo airport where more than 60% of Juju-bound flights departure. Although the simulation model needs to be calibrated and validated for the real-world application, the results clearly shows that the approach can possibly implemented as a tool for preparing the daily plan at the pre-tactical stage defined in the ICAO ATFM manual.