• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 추계학술대회 논문집
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• pp.345-346
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• 2012

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2012년도 춘계학술대회 논문집
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• pp.381-382
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• 2012

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.1223-1224
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• 2013

• 마이크로전자및패키징학회지
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• 제21권1호
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• pp.31-39
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• 2014

최근 모바일 응용 제품에 사용되는 반도체 패키지는 고밀도, 초소형 및 다기능을 요구하고 있다. 기존의 웨이퍼 레벨 패키지(wafer level package, WLP)는 fan-in 형태로, I/O 단자가 많은 칩에 사용하기에는 한계가 있다. 따라서 팬 아웃 웨이퍼 레벨 패키지(fan-out wafer level package, FOWLP)가 새로운 기술로 부각되고 있다. FOWLP에서 가장 심각한 문제 중의 하나는 휨(warpage)의 발생으로, 이는 FOWLP의 두께가 기존 패키지에 비하여 얇고, 다이 레벨 패키지 보다 휨의 크기가 매우 크기 때문이다. 휨의 발생은 후속 공정의 수율 및 웨이퍼 핸들링에 영향을 미친다. 본 연구에서는 FOWLP의 휨의 특성과 휨에 영향을 미치는 주요 인자에 대해서 수치해석을 이용하여 분석하였다. 휨을 최소화하기 위하여 여러 종류의 epoxy mold compound (EMC) 및 캐리어 재질을 사용하였을 경우에 대해서 휨의 크기를 비교하였다. 또한 FOWLP의 주요 공정인 EMC 몰딩 후, 그리고 캐리어 분리(detachment) 공정 후의 휨의 크기를 각각 해석하였다. 해석 결과, EMC 몰딩 후에 발생한 휨에 가장 영향을 미치는 인자는 EMC의 CTE이며, EMC의 CTE를 낮추거나 Tg(유리천이온도)를 높임으로서 휨을 감소시킬 수 있다. 캐리어 재질로는 Alloy42 재질이 가장 낮은 휨을 보였으며, 따라서 가격, 산화 문제, 열전달 문제를 고려하여 볼 때 Alloy 42 혹은 SUS 재질이 캐리어로서 적합할 것으로 판단된다.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2002년도 International Symposium
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• pp.219-225
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• 2002

This paper presents a novel "bumpless flip chip package"for cost! performance driven devices. Using the conventional electroplating and etching processes, this package enables the production of fine pitch BGA up to 256 I/O with single layer routing. An array of circuitry down to $25-50{\mu}{\textrm}{m}$ line/space is fabricated to fan-in and fan-out of the bond pads without using bumps or substrate. Various types of joint methods can be applied to connect the fine trace and the bond pad directly. The resin-filled terminal provides excellent compliancy between package and the assembled board. More interestingly, the thin film routing is similar to wafer level packaging whereas the fan-out feature enables high lead count devices to be accommodated in the BGA format. Details of the design concepts and processing technology for this novel package are discussed. Trade offs to meet various cost or performance goals for selected applications are suggested. Finally, the importance of design integration early in the technology development cycle with die-level and system-level design teams is highlighted as critical to an optimal design for performance and cost.

• 반도체디스플레이기술학회지
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• 제18권1호
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• pp.65-69
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• 2019

The cure properties of ethoxysilyl diglycidyl isocyanurate(Ethoxysilyl-DGIC) and ethylsilyl diglycidyl isocyanurate (Ethylsilyl-DGIC) epoxy resin systems with a phenol novolac hardener were investigated for anticipating fan out-wafer level package(FO-WLP) applications, comparing with ethoxysilyl diglycidyl ether of bisphenol-A(Ethoxysilyl-DGEBA) epoxy resin systems. The cure kinetics of these systems were analyzed by differential scanning calorimetry with an isothermal approach, and the kinetic parameters of all systems were reported in generalized kinetic equations with diffusion effects. The isocyanurate type epoxy resin systems represented the higher cure conversion rates comparing with bisphenol-A type epoxy resin systems. The Ethoxysilyl-DGIC epoxy resin system showed the highest cure conversion rates than Ethylsilyl-DGIC and Ethoxysilyl-DGEBA epoxy resin systems. It can be figured out by kinetic parameter analysis that the highest conversion rates of Ethoxysilyl-DGIC epoxy resin system are caused by higher collision frequency factor. However, the cure conversion rate increases of the Ethylsilyl-DGEBA comparing with Ethoxysilyl-DGEBA are due to the lower activation energy of Ethylsilyl-DGIC. These higher cure conversion rates in the isocyanurate type epoxy resin systems could be explained by the improvements of reaction molecule movements according to the compact structure of isocyanurate epoxy resin.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.124-130
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• 2023

Recently, fan out wafer level packaging, which enables high integration, miniaturization, and low cost, is being rapidly applied in the semiconductor industry. In particular, FOWLP is attracting attention in the mobile and Internet of Things fields, and is recognized as a core technology that will lead to technological advancements such as 5G, self-driving cars, and artificial intelligence in the future. However, as chip density and package size within the package increase, FOWLP warpage is emerging as a major problem. These problems have a direct impact on the reliability and electrical performance of semiconductor products, and in particular, cause defects such as vacuum leakage in the manufacturing process or lack of focus in the photolithography process, so technical demands for solving them are increasing. In this paper, warpage simulation according to the thickness of FOWLP material was performed using finite element analysis. The thickness range was based on the history of similar packages, and as a factor causing warpage, the curing temperature of the materials undergoing the curing process was applied and the difference in deformation due to the difference in thermal expansion coefficient between materials was used. At this time, the stacking order was reflected to reproduce warpage behavior similar to reality. After performing finite element analysis, the influence of each variable on causing warpage was defined, and based on this, it was confirmed that warpage was controlled as intended through design modifications.

• 동력기계공학회지
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• 제16권4호
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• pp.51-59
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• 2012

The computational flow analysis using LES technique was carried out to investigate the flow characteristics of a sirocco fan under the maximum flowrate condition. The commercial SC/Tetra software was used for this unsteady and three-dimensional numerical analysis. In consequence, because a flow is unstable within the range of about 50% of a housing depth from a bellmouth around the cutoff region, the passing flow through the blade cascade occurred on the X-Y plane is a slow or a reverse with approaching to the housing inlet. Also, the secondary flow shows on the radial plane of a housing, and its vortex center exists within about 33% of a housing depth from a bellmouth except the cutoff region. Moreover, the flow occurring on the exit plane of a sirocco fan shows a complex secondary flow.

• 한국전산유체공학회지
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• 제21권3호
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• pp.39-47
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• 2016

We conducted a multi-stage optimization to secure the desired performance of a centrifugal fan for home appliance in an early stage of product development. In optimization, the static pressure at the outlet of the fan is chosen as an objective function that is to be maximized, providing the required flow rate at the operating point of the fan. The optimization procedure begins with parameters for an initial baseline fan design. The baseline design is optimized by using a commercial optimization package. Accordingly, the corresponding blade models with a set of geometrical parameters are generated. Flow through a fan is simulated by solving the Reynolds-averaged Navier-Stokes equations. A multi-stage optimization scheme is employed to determine the family of optimum values for the parameters, leading to the pressure increase at the outlet of the fan. To validate the numerically obtained optimal design parameters, we fabricated the three types of fans using rapid prototyping and assessed the performance using a fan tester. Experimental results show that the design parameters at each stage satisfy the goal of optimization. The multi-stage optimization process turned out to be a useful tool in the development of a centrifugal fan.

• 마이크로전자및패키징학회지
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• 제26권1호
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• pp.29-33
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• 2019

전자패키지 크기의 소형화와 전자기기의 성능 향상이 함께 이루어지면서 높은 입출력 밀도 구현이 중요한 요소로서 평가받고 있다. 이를 구현하기 위해 팬아웃 웨이퍼 레벨 패키지(FO-WLP)가 큰 주목을 받고 있다. 하지만 FO-WLP는 휨(Warpage) 현상에 취약하다는 약점이 있다. 휨 현상은 생산 수율 감소와 더불어 패키지 신뢰성 하락에 큰 원인이므로 이를 최소화하는 것이 필수적이다. 유한요소해석을 이용한 재질의 물성 등 FO-WLP의 휨 현상과 연관된 요소에 대한 많은 연구가 진행되어 왔지만, 대부분의 연구는 이러한 요소들의 불확실성을 고려하지 않았다. 재질의 물성, 칩의 위치 등 패키지의 휨 현상과 연관된 요소들은 제조 측면에서 보았을 때 불확실성을 가지고 있기 때문에, 실제 결과와 더 가깝게 모사하기 위해서는 이러한 요소들의 불확실성이 고려되어야 한다. 이번 연구에서는 FO-WLP 과정 중 칩의 탄성 계수가 정규 분포를 따르는 불확실성을 가졌을 때 휨 현상에 미치는 영향을 유한요소해석을 통해 알아보았다. 그 결과 칩의 탄성 계수의 불확실성이 최대 von Mises 응력에 영향을 미치는 것을 확인하였다. Von Mises 응력은 전체 패키지 신뢰성과 관련된 인자이기 때문에 칩의 물성에 대한 불확실성 제어가 필요하다.