• Journal of Digital Contents Society
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• v.7 no.1
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• pp.35-40
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• 2006

Game AI(Artificial Intelligence) technologies implement the movement of autonomous characters and control the movement of Non-Player Characters(NPC). In this paper, we present several types of game AI control systems such as Movement Scripts, FSM(Finite State Machines), Hierarchical State Machines, fuzzy State Machines, and Pathfinding techniques and their limitations.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.251-257
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• 2014

The Viterbi algorithm(VA) is used to estimate the state transition of discrete-time finite state machine(FSM) that is in an uncorrelated noisy environment. This paper modified the Hamming Network to estimate the state transitions in the finite state machines, and proposed state-parallel and block-parallel Viterbi decoder. The modified Hamming Network(mHN) can perform the decoding of convolutional codes correctly as conventional Viterbi decoder. Furthermore, the complexities of the proposed Viterbi decoder are reduced approximately 10% less than conventional Viterbi decoder, and the processing times are improved approximately 40% more than conventional Viterbi decoder.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.781-784
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• 1993

Most linguistic models of processes or plants known are essentially static, that is, time is not a parameter in describing the behavior of the object's model. In this paper we show two models for synchronous finite state machines (FSM) based on fuzzy logic, namely the Crisp-State-Fuzzy-Output (CSFO FSM) and Fuzzy-State-Fuzzy Output (FSFO FSM). As a result of the introduction of the FSM models, the improved architectures for fuzzy logic controller have been defined. These architectures featuring pipelined intelligent fuzzy controller are discussed in terms of dimensionality of the model. VLSI integrated circuit implementation issues of the fuzzy logic controller are also considered. The presented approach can be utilized for fuzzy controller hardware accelerators intended to work in the real-time environment.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.11a
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• pp.481-484
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• 2004

가상현실에 생성되는 NPC(Non-Player Character)의 인공지능을 설계하는 AI 디자이너가NPC 행동 패턴을 효율적으로 모델링을 할 수 있게 도와주는 FSM(Finite-State Machines) 도구를 제시한다. 이 도구는 FSM 각 상태와 상태의 변이에 따른 여러 가지 행동 패턴을 쉽게 모델링 할 수 있으며, AI를 디자인하는 디자이너가 가상현실 속에 존재하는 NPC의 AI를 설계 하고 프로그래머가 AI를 구현하는데 필요한 시간을 줄여준다. 또한 행동 패턴의 FSM 구조가 일반화되어 재사용성이 높아질 뿐만 아니라 AI를 하드코딩으로 구현 하는 것을 방지 할 수 있다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1906-1915
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• 1990

A synthesis system generating sequential circuits from a high-level hardware descdription language CHDL, modelling language for Thor functional/behavioral simulator, is developed. In this paper, we describe the semantic analysis process, state minimization and state assignment algorithms. proposed assignment algorithm generates optimal state vectors using constraint matrix and similarity graph. Expremental results for MCNC benchmarks, standard test circuits, show that the system inplementing the proposed algorithms can be a viable tool for designing large finite state machines.

• Journal of KIISE:Software and Applications
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• v.35 no.1
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• pp.12-21
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• 2008

As the usage of computer systems is increasing in our lives, the reliability and safely of these systems need to be thoroughly checked through the verification techniques. As a basic formalism for several modeling methods, the finite state machine (FSM) is widely used in specification and verification of system models. And there is a technique for ing internal events of FSM in order to effectively analyze the system. However, this technique does not handle the state explosion problem since it can be applied after completely generating all the state space of the system. In this research, we provide a new approach for efficiently representing concurrent properties of FSM, the slice model and provide an efficient transition reduction method based on the slice model. Our approach is effective in time and space perspective since it is peformed by partially generating the needed system states while the existing abstraction technique can be applied to all the system states.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.5
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• pp.59-68
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• 2005

A novel immunotronic approach to fault detection in hardware based on symbiotic evolution is proposed in this paper. In the immunotronic system, the generation of tolerance conditions corresponds to the generation of antibodies in the biological immune system. In this paper, the principle of antibody diversity, one of the most important concepts in the biological immune system, is employed and it is realized through symbiotic evolution. Symbiotic evolution imitates the generation of antibodies in the biological immune system morethan the traditional GA does. It is demonstrated that the suggested method outperforms the previous immunotronic methods with less running time. The suggested method is applied to fault detection in a decade counter (typical example of finite state machines) and MCNC finite state machines and its effectiveness is demonstrated by the computer simulation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.2
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• pp.137-144
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• 2001

In this paper, a state assignment algorithm was proposed to reduce power consumption in control-flow oriented finite state machines. The Markov chain model is used to reduce the switching activities, which closely relate with dynamic power dissipation in VLSI circuits. Based on the Markov probabilistic description model of finite state machines, the hamming distance between the codes of neighbor states was minimized. To express the switching activities, the cost function, which also accounts for the structure of a machine, is used. The proposed state assignment algorithm is tested with Logic Synthesis Benchmarks, and reduced the cost up to 57.42% compared to the Lakshmikant's algorithm.

• International Journal of Computer Science & Network Security
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• v.21 no.7
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• pp.233-240
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• 2021

The majority of the Web's success can be related to its productivity and flexibility. Web Services (WSs) have the means to create new patterns for the delivery of software capabilities. The WS easily provides the use of existing components available via the Internet. WSs are a new trend that shares ubiquitous systems with others, so the popularity of the Web is increased day by day with their associated systems. This paper will explore and adopt the possibility of developing a technique that will automate instructors' scheduling of timetables within a Web services environment. This technique has an advantage that facilitates users to reduce the time cost and effort by reducing errors and costs for institutes. Providing dependable tables to avoid mistakes related to instituting schedules is ensured by an automated repetitive manual procedure. Automated systems are increasingly developed based on organizations and their customers. Still, the setting's difficulty of automation systems increases to rise as the system architecture and applications must accomplish various requirements and specifications of ever-demanding project scenarios. The automation system is composed of an operating system, platforms, devices, machines, control system, and information technology. This architecture provides more productivity and optimized services. The main purpose of this paper is to apply an automation system to enhance both quality and productivity. This paper also covers an agile method of proving an automation system by Finite State Machine (FSM) and Attributed Graph Grammar (AGG) tool.

• Journal of KIISE:Software and Applications
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• v.30 no.7_8
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• pp.642-648
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• 2003

In this paper, we are interested in checking equivalence of FSMs(finite state machines). Two FSMs are equivalent if and only if their responses are always equal with each other with respect to the same external stimuli. Equivalence checking FSMs makes complicated FSM be substituted for simpler one, if they are equivalent. We can also determine the system satisfies the requirements, if they are all written in FSMs. In this paper, we regard equivalence checking problem as model checking one. For doing so, we construct the product model $M ={M_A} {\beta}{M_B} from two FSMs ${M_A} and {M_B}$. And we also get the temporal logic formula ${\Phi}$ from the equivalence checking definition. Then, we can check with model checker whether if satisfies ${\Phi}$, written $M= {.\Phi}$. Two FSMs are equivalent, if $M= {.\Phi}$ Otherwise, it is not equivalent. In that case, model checker generates counterexamples which explain why FSMs are not equivalent. In summary, we solve the equivalence checking problem with model checking techniques. As a result of applying to several examples, we have many satisfiable results.