• 디지털산업정보학회논문지
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• 제9권2호
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• pp.55-61
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• 2013

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare). Contemporary FPGAs have large resources of logic gates and RAM blocks to implement complex digital computations. In this paper, we implement a system of digital instrumentation using FPGA. This system consists of the trigger part, memory address controller part, control FSM part, Encoder part, LCD controller part. The hardware implement using FPGA and the verification of the operation is done in a PC simulation. The proposed hardware was mapped into Cyclone III EP2C5Q208 from Altera and used 1,700(40%) of Logic Element (LE). The implemented circuit used 24,576-bit memory element with 6-bit input signal. The result from implementing in hardware (FPGA) could operate stably in 140MHz.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제9권5호
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• pp.560-566
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• 2003

최근까지 초고집적 FPGA 혹은 재구성가능 프로세서 등을 이용한 RC(재구성 컴퓨팅) 기술에 대한 많은 연구가 진행되어 왔으며, 최근 들어서는 이와 같은 RC 기술을 응용분야에 실제 적용한 성공적인 상용화 사례들이 보고되고 있다. 본 논문에서는 FPGA의 동적 재구성 기능과 RC 기법을 이용하여 DES 암호화 시스템을 적은 용량의 FPGA에 구현하기 위한 설계와 구현된 DES 암호화 시스템의 시스템수준 검증 기법을 제안한다. 이를 통하여 동적 재구성 기반의 접근법이 가지는 유용성을 평가할 수 있었는데, 그것은 FPGA의 동적 재구성을 통하여 임의의 알고리즘의 RC 기법에 의한 하드웨어 구현에 있어서 성능과 가격간의 타협이 매우 효과적으로 이루어 질 수 있다는 것이다.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제8권6호
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• pp.717-726
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• 2002

본 연구에서는 최근 미국표준기술연구소(NIST)에 의해 암호화 표준 알고리즘으로 채택된 AES 알고리즘을 Altera FLEX10KE 계열의 하드웨어로 구현하는 여러 가지 방법들에 대하여 VHDL 설계를 이용하여 전반적으로 분석하였다. 구현 방법들로는 기본 구조, 루프 언롤링, 라운드 내부 파이프라이닝, 라운드 외부 파이프라이닝, 그리고 5-box의 자원 공유 등을 사용하였다. 이 연구에서 VHDL 설계 및 시뮬레이견은 Altera 사의 Maxplus2 9.64를 이용하였으며, FPGA는 Altera 사의 FLEX10KE 계열을 사용하였다. 결과에 따르면, 4-단계 라운드 내부 파이프라이닝 구현 방법이 성능대가격비 면에서 가장 우수한 것으로 나타난 반면에, 루프 언롤링 방법이 가장 뒤떨어지는 것으로 나타났다.

• 한국통신학회논문지
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• 제23권9A호
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• pp.2141-2152
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• 1998

본 논문에서는 ISM 밴드 규정에의한 미약 전파를 사용하여 신뢰성 있는 데이터 전송을 할 수 있는 실내용 무선 모뎀을 설계하고 구현하였다. 동기식 BPSK 및 QPSK 변복조 방식에 의한 DS-SS(직접시퀀스대역확산) 신호 방식과 길쌍 부호 및 비터비 복호 방식을 사용하였다. RF 링크는 900 MHz 대역에서 FDD(Frequency Devision D Duplexing) 방식에 의한 변복조를 하였고 디지털 신호처리 회로는 ASIC화가 가능하도록 FPGA로 구현하였다. 자체 설계한 디지털 정합 필터와 결정 로직(decision logic)으로 구성된 새로운 구조의 동기 포착 및 추적 회로의 성능을 실험을 통해 확인하였으며, 이 모뎀을 PC의 RS-232C 포트에 접속한 전체 시스템을 실내 환경에서 운영하여 파일 전송이 가능함을 확인하였다.

• 제어로봇시스템학회논문지
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• 제21권8호
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• pp.742-747
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• 2015

The quality of steel plate products is determined by the number of defects and the process problems are estimated by shapes of defects. Therefore pinholes defects of cold rolled steel have to be controlled. In order to improve productivity and quality of products, within each production process, the product is inspected by an adequate inspection system individually in the lines of steelworks. Among a number of inspection systems, we focus on the pinholes detection system. In this paper, we propose an embedded system using FPGA which can detect pinholes defects. The proposed system is smaller and more flexible than a traditional system based on expensive frame grabbers and PC. In order to detect consecutive defects, FPGAs acquire two dimensional image and process the image in real time by using correlation of lines. The proposed pinholes detection algorithm decreases arithmetic operations of image processing and also we designed the hardware to shorten the data path between logics due to decreasing propagation delay. The experimental results show that the proposed embedded system detects the reliable number of pinholes in real time.

• 한국전자파학회논문지
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• 제14권11호
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• pp.1134-1142
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• 2003

본 논문은 STS(Space Time Spreading) 다이버시티 기능을 지원하는 시스템을 FPGA(Field Programmable Gate Array)를 이용하여 구현하고, 이 시스템을 구성하고 있는 각 모듈의 기능과 실제 설계 방법을 소개한다. 본 논문에서 구현한 개루프 전송 다이버시티 시스템인 STS 시스템의 성능을 개선하기 위해서는 페이딩 환경에 따라 변화하는 통신채널의 정확한 검출이 필수적이다. 이를 위하여 파일럿 패널의 정확한 검출을 위한 최적의 망각인자(Forgetting factor)를 제안한다. 본 논문에서 구현한 STS 시스템과 컴퓨터 시뮬레이션을 통하여 CDMA2000 1x 신호환경에서 STS 시스템 적용시 도플러 주파수 80 Hz일 경우에 0.7의 값을 가지는 망각인자를 사용하여 각 구간의 페이딩을 검출함으로써 파일럿 신호의 전력이 충분하지 않을 경우에도 적분 구간을 많이 늘릴 필요 없이 파일럿 채널을 검출할 수 있음을 알 수 있었다.

• ETRI Journal
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• 제42권2호
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• pp.205-216
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• 2020

An arbiter physical unclonable function (APUF) has exponential challenge-response pairs and is easy to implement on field-programmable gate arrays (FPGAs). However, modeling attacks based on machine learning have become a serious threat to APUFs. Although the modeling-attack resistance of an MA-APUF has been improved considerably by architecture modifications, the response generation method of an MA-APUF results in low uniqueness. In this study, we demonstrate three design problems regarding the low uniqueness that APUF-based strong PUFs may exhibit, and we present several foundational principles to improve the uniqueness of APUF-based strong PUFs. In particular, an improved MA-APUF design is implemented in an FPGA and evaluated using a well-established experimental setup. Two types of evaluation metrics are used for evaluation and comparison. Furthermore, evolution strategies, logistic regression, and K-junta functions are used to evaluate the security of our design. The experiment results reveal that the uniqueness of our improved MA-APUF is 81.29% (compared with that of the MA-APUF, 13.12%), and the prediction rate is approximately 56% (compared with that of the MA-APUF (60%-80%).

• ETRI Journal
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• 제33권5호
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• pp.731-740
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• 2011

Reconfigurable computing using a field-programmable gate-array (FPGA) device has become a promising solution in system design because of its power efficiency and design flexibility. To bring the benefit of FPGA to many application programmers, there has been intensive research about automatic translation from high-level programming languages (HLL) such as C and C++ into hardware. However, the large gap of syntaxes and semantics between hardware and software programming makes the translation challenging. In this paper, we introduce a new approach for the translation by using the widely used GCC compiler. By simply adding a hardware description language (HDL) backend to the existing state-of- the-art compiler, we could minimize an effort to implement the translator while supporting full features of HLL in the HLL-to-HDL translation and providing high performance. Our translator, called GCC2Verilog, was implemented as the GCC's cross compiler targeting at FPGAs instead of microprocessor architectures. Our experiment shows that we could achieve a speedup of up to 34 times and 17 times on average with 4-port memory over PICO microprocessor execution in selected EEMBC benchmarks.

• IEIE Transactions on Smart Processing and Computing
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• 제4권4호
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• pp.237-250
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• 2015

This paper describes a hardware-oriented algorithm and its conceptual implementation in a real-time speed limit traffic sign detection system on an automotive-oriented field-programmable gate array (FPGA). It solves the training and color dependence problems found in other research, which saw reduced recognition accuracy under unlearned conditions when color has changed. The algorithm is applicable to various platforms, such as color or grayscale cameras, high-resolution (4K) or low-resolution (VGA) cameras, and high-end or low-end FPGAs. It is also robust under various conditions, such as daytime, night time, and on rainy nights, and is adaptable to various countries' speed limit traffic sign systems. The speed limit traffic sign candidates on each grayscale video frame are detected through two simple computational stages using global luminosity and local pixel direction. Pipeline implementation using results-sharing on overlap, application of a RAM-based shift register, and optimization of scan window sizes results in a small but high-performance implementation. The proposed system matches the processing speed requirement for a 60 fps system. The speed limit traffic sign recognition system achieves better than 98% accuracy in detection and recognition, even under difficult conditions such as rainy nights, and is implementable on the low-end, low-cost Xilinx Zynq automotive Z7020 FPGA.

• 대한전기학회논문지:시스템및제어부문D
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• 제49권2호
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• pp.81-87
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• 2000

This paper presents a new approach to the synthesis of two-dimensional arrays such as Atmel 6000 series FPGAs using internal don't cares. Basically complex terms which fits to the linear array of cells without further routing wires are generated and they are collected by OR/XOR operations. In previous methods, complex terms are collected only by XOR operations, which may not be effective for nearly unate functions. In this paper, we allow complex terms to be collected by OR operations in addition to XOR operations. First, complex terms that lies in the ON-set of the function are generated and collected by OR operations. The sub-function realized by the first stage becomes an internal don't cares and they are exploited in the second stage which generates complex terms collectable by XOR operation. Experimental results shows the efficacy of the proposed method compared to the previous methods.