• Journal of IKEEE
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• v.18 no.4
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• pp.566-571
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• 2014

A safety class field programmable gate array based system in nuclear power plant has been developed to improve the diversity. Testbench is necessary to satisfy the technical reference, IEC-62566, for verification and validation of register transfer level code. We use the open verification methodology(OVM) developed by standard body. We show that our testbench can use random input for test. And also we show that reusability of block level testbench for the integration level testbench, which is very efficient for large scale system like nuclear reactor protection system.

• Journal of Internet of Things and Convergence
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• v.6 no.1
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• pp.97-102
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• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.2
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• pp.293-298
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• 2009

In this contribution, a 193-bit elliptic curve cryptography coprocessor was implemented on an FPGA board. Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP which was double-checked in view of hardware structure together with algoritunic verification, was implemented on the Altera CycloneII FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2380-2388
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• 2015

A hardware implementation of MOD(moving object detection) algorithm using EGML(effective Gaussian mixture learning)- based background subtraction to detect moving objects in video is described. Some approximations of EGML calculations are applied to reduce hardware complexity, and pipelining technique is adopted to improve operating speed. The MOD processor designed in Verilog-HDL has been verified by FPGA-in-the-loop verification using MATLAB/Simulink. The MOD processor has 2,218 slices on the Virtex5-XC5VSX95T FPGA device and its throughput is 102 MSamples/s at 102 MHz clock frequency. Evaluation results of the MOD processor for 12 images in the IEEE CDW-2012 dataset show that the average recall value is 0.7631, the average precision value is 0.7778 and the average F-measure value is 0.7535.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.68-73
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• 2006

This, paper proposes a cosimulation methodology that results in an efficient SoC design as well as fast verification by integrating HDL, SystemC, and algorithm-level abstraction using the design tools Active-HDL and Matlab's Simulink. To demonstrate the proposed design methodology, we implemented the design technique on a serial connection multi-channel speaker system. We have demonstrated the proposed cosimulation method utilizing an ARM processor based SoC Master board with the AMBA bus interface and a Xilinx Vertex4 FPGA. The proposed method has the advantage of simultaneous simulation verification of both software and hardware parts in high levels of abstraction mixed with some performance critical parts in more concrete RTL codes. This allows relatively fast and easy design of a speaker connection system which typically requires significant amount of data processing for verification.

• Journal of IKEEE
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• v.15 no.1
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• pp.86-95
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• 2011

In this paper, we propose a testbed system for the crisis management system of the power grid(CMS-PG) using satellite communication network. For the verification of CMS-PG, the proposed system composed of the simulator of satellite communication network and the simulator of phase measurement unit. Proposed satellite communication simulator can evaluate the delay and the robustness of the communication according to the rainfall and the humidity of local site. And the proposed simulator can calculates the voltage stability by hardware implementation using FPGA. Using the proposed testbed system, we adapted its function of crisis management system for the conventional power grid.

• Smart Structures and Systems
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• v.14 no.6
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• pp.1151-1172
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• 2014

This paper presents a user programmable computational/control platform developed to conduct real-time hybrid simulation (RTHS). The architecture of this platform is based on the integration of a real-time controller and a field programmable gate array (FPGA).This not only enables the user to apply user-defined control laws to control the experimental substructures, but also provides ample computational resources to run the integration algorithm and analytical substructure state determination in real-time. In this platform the need for SCRAMNet as the communication device between real-time and servo-control workstations has been eliminated which was a critical component in several former RTHS platforms. The accuracy of the servo-hydraulic actuator displacement control, where the control tasks get executed on the FPGA was verified using single-degree-of-freedom (SDOF) and 2 degrees-of-freedom (2DOF) experimental substructures. Finally, the functionality of the proposed system as a robust and reliable RTHS platform for performance evaluation of structural systems was validated by conducting real-time hybrid simulation of a three story nonlinear structure with SDOF and 2DOF experimental substructures. Also, tracking indicators were employed to assess the accuracy of the results.

• Journal of Internet Computing and Services
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• v.3 no.5
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• pp.9-17
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• 2002

CSIX-L1 is the Common Switch Interface that defines a physical interface for transferring information between a traffic manager (Network Processor) and a switching fabric in ATM, IP, MPLS, Ethernet and data communication areas. In Tx, data to be transmitted is generated in Cframe which is the base information unit and in Rx, original data is extracted from the received Cframe. CSIX-L1 suppots the 32, 64, 96, and 123-bit interface and generates a variable length CFrame and Idle Cframe. Also CSIX-L1 appends Padding byte and supports 16-bit Vertical parity, CSIX-L1 is designed using Xilinx 4,1i. After functional and timing simulations are completed. CSIX-L1 module is downloaded in Xilinx FPGA XCV1000EHQ240C and verified. The synthesized CSIX module operates at 27MHz.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.12
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• pp.2632-2640
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• 2011

In this paper, we implemented a memory controller which can accommodate data processing blocks. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Interface, Master Arbitrator, Memory Interface, Memory accelerator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.7
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• pp.83-90
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• 2004

This paper describes on-board decentralized data acquisition system that acquires and encodes the numerous sensor data distributed on the big flight vehicles efficiently. The system's sub-units which have one encoder unit and several remote units were designed and simulated according to the communication protocols and the control, sequence logics based on the FPGA chip. And we have made the functional verification of the acquisition, collection and formatting of remote analog and digital data for the manufactured hardwares.