• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.3 s.303
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• pp.65-72
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• 2005

This paper proposes an image display system that reduces the core performance of the processor allocated in the image display, thereby enabling the use of a less expensive processor with a low performance. Essentially, the proposed system supports an image display function for a high resolution in the module of an electronic picture frame (EPF) using a low-performance processor based on converting high definition (HD) image data at a 15Hz frame rate into HD image data at a 60Hz frame rate for use in a digital TV system. As a result, the proposed system can reduce the processor performance to a level corresponding to an image display with a low frame rate, thereby reducing the product cost and allowing various additional functions. Finally, the proposed system is implemented to confirm effectiveness.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.5C
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• pp.454-464
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• 2002

In the ATM-PON (Asynchronous Transfer Mode-Passive Optical Network), the downstream cell transmitted by an OLT is broadcast to all ONUs. The ONU receives selectively its own cells by VP filtering. On the other hand, the upstream cell can be transmitted by ONU in the case of receiving a grant from the OLT. After providing the grant to an ONU, the OLT expects the arrival of a cell after an elapse of the equalized round trip delay. ITU-T G.983.1 recommends that one bit error is allowed between the expected arrival time and the actual arrival time at the OLT. Because the ONU processes the different delay to each type of grant (ranging, user cell, and mimi-slot grant), it is not simple to design the transmission part of ONU. In this paper, we implement a grant processor which provides the delay accurately in the ONU TC chip with the FPGA. For the given equalized delay, it deals with the delay for the cell, the byte, and the bit unit by using the shift register, the byte counter, and the D flip-flop, respectively. We verify the operation of the grant processor by the time simulation and the measurement of the optical board output.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.4A
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• pp.387-393
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• 2008

In this paper, we present an SDR (Software Defined Radio) handset modem platform which supports communication systems such as HSDPA (High Speed Downlink Packet Access), and WiBro (Wireless Broadband Portable Internet). The proposed SDR platform employs DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), and microprocessors in such a way that the various communication functions like HSDPA and WiBro can be programmed and downloaded to the hardware platform. The proposed SDR platform can be used for functional verification of the physical layers of the mobile handset system in the mobile communication network. We first demonstrate the receiving structure of the physical layer of the HSDPA and WiBro system. Then, the hardware implementation of the proposed SDR platform is shown with functions and optimized signal flows required at each mode. Finally, the link performance of each mode operating on the proposed SDR platform is presented through the internal loopback tests with the test vectors. The experimental performance has been compared with the computer simulation results.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2002.09a
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• pp.468-470
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• 2002

We have designed X-ray detection system and multi-channel data acquisition system for Spiral CT application. X-ray detection system consists of scintillator and photodiode. Scintillator converts X-ray into visible light. Photodiode converts visible light into electrical signal. The multi-channel data acquisition system consists of analog, digital, master and backplane board. Analog board detects electrical signal and amplifies signal by 140dB. Digital board consists of MUX(Multiplex) which routes multi-channel analog signal to preamplifier, and ADC(Analog to Digital Converter) which converts analog signal into digital signal. Master board supplies the synchronized clock and transmits the digital data to image reconstructor. Backplane provides electrical power, analog output and clock signal. The system converts the projected X-ray signal over the detector array with large gain, samples the data in each channel sequentially, and the sampled data are transmitted to host computer in a given time frame. To meet the timing limitation, this system is very flexible since it is implemented by FPGA(Field Programmable Gate Array). This system must have a high-speed operation with low noise and high SNR(signal to noise ratio), wide dynamic range to get a high resolution image.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.9
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• pp.135-140
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• 2015

Web-services employ XML that is the well-formed structure as a de-facto standard to represent data. SOAP or REST is one of the representative web-services using XML based massage passing systems. The XML parser can be divided into event driven and DOM tree. A streaming parser as an event driven is widely used for high-speed parsing. Since the streaming parser processes XML documents in sequence, they have any limitation to improve system performance. In order to improve speed of streaming XML parser, we present multibyte based streaming XML hardware parser using the element analyzer instead of the state machine. Compared to other parsers, the proposed MStreXHP can achieve about 2.72 times improvement in the number of clock cycles to be consumed in comparison of characters and sustain about 7.8Gbps throughput. Therefore, our MStreXHP is desirable for the streaming XML hardware parser on high-performance systems.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.639-644
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• 2011

By the development of the information superhighway, the current data communication system can be exchanged data quickly and precisely between subscribers. In this paper, LVTTL(Low Voltage Transistor Transistor Logic), Using the fundamental one logic at several kinds of used in communication systems, the LVTTL transmission characteristics were measured by according to the change data transfer rate and the transmission line length. Because the transmission line length required on the current system is 30cm, We analysed LVTTL data transfer characteristics according to the transmission line length required on the current system. The amplitude level of LVTTL at 10Mbps is 3V and 50Mbps is 2.2V and 100Mbps is 2V and 125Mbps is 1.5V and 150Mbps is 1.4V. The length of transmission line 30cm was stable state up to 100Mbps data transfer rate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2628-2635
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• 2010

This paper analyzes the detection probability of FMCW (Frequency Modulated Continuous Wave) radar based on Doppler frequency and analog-digital converter bit and designs and implements signal processing part of FMCW radar. For performance evaluation, the FMCW radar system consists of a transmitted part and a received part and uses AWGN channel. The system model is verified through analysis and simulation. Frequency offset occurs in the received part caused by the mismatching between the received signal and the reference signal. In case of Doppler frequency less than about 38KHz, performance degradation of detection does not occur in FMCW radar with 75cm resolution The analog-digital converter needs at least 6 bit in order not to degrade the detection probability. And, we design and implement digital signal processing part based on DDS chip of digital transmitted signal generator for FMCW radar.

• Proceedings of the KSRS Conference
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• 2002.10a
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• pp.587-592
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• 2002

A new digital correlator fur an airborne synthetic aperture radiometer was designed in order to replace the conventional analog correlator unit which will become very complicated while the number of channels is increasing. The digital correlator uses digital IQ demodulator instead of the intermediate frequency (IF) phase shifter to make the correlation processing performed digitally at base band instead of analogly at IF. This technique has been applied to the digital receiver in softradio. The down-converted IF signals from each pair of receiver channels become low rate base-band digital signals after under-sampled, Digitally Down-Converted (DDC), decimated and filtered by FIR filters. The digital signals are further processed by two digital multipliers (complex correlation), the products are integrated by the integrators and finally the outputs from the integrators compose of the real part and the imaginary part of a sample of the visibility function. This design is tested by comparing the results from digital correlators and that from analog correlators. They are agreed with each other very well. Due to the fact that the digital correlators are realized with the help of Analog-Digital Converter (ADC) chips and the FPGA technology, the realized volume, mass, power consumption and complexity turned out to be greatly reduced compared with that of the analog correlators. Simulations show that the resolution of ADC has an influence on the synthesized antenna patterns, but this can be neglected if more than 2bit is used.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.20 no.12
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• pp.136-144
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• 2021

The purpose of this study was to develop and verify a precision transmission error measurement system for a gear pair. The transmission error measurement system of the gear pair was developed as a measurement unit, signal processing unit, and signal analysis unit. The angular displacement for calculating the transmission error of the gear pair was measured using an encoder. The signal amplification, interpolation, and transmission error calculation of the measured angular displacement were conducted using a field-programmable gate array (FPGA) and a real-time processor. A high-pass filter (HPF) was applied to the calculated transmission error from the real-time processor. The transmission error measurement test was conducted using a gearbox, including the master gear pair. The same test was repeated three times in the clockwise and counterclockwise directions, respectively, according to the load conditions (0 - 200 N·m). The results of the gear transmission error tests showed similar tendencies, thereby confirming the stability of the system. The measured transmission error was verified by comparing it with the transmission error analyzed using commercial software. The verification showed a slight difference in the transmission error between the methods. In a future study, the measurement and analysis method of the developed precision transmission error measurement system in this study may possibly be used for gear design.