Design and Implementation of Image Display Module for Low-cost High Definition Television

저가의 HDTV를 위한 영상출력 모듈의 설계 및 구현

  • Choi Jae-Seung (Digital Technology Research Center, Kyungpook National University) ;
  • Kim Ick-Hwan (LG Electronics) ;
  • Nam Jae-Yeal (Dept. of Computer Engineering, Keimyung University) ;
  • Ha Yeong-Ho (School of Electrical Engineering and Computer Science, Kyungpook National University)
  • Published : 2005.05.01

Abstract

This paper proposes an image display system that reduces the core performance of the processor allocated in the image display, thereby enabling the use of a less expensive processor with a low performance. Essentially, the proposed system supports an image display function for a high resolution in the module of an electronic picture frame (EPF) using a low-performance processor based on converting high definition (HD) image data at a 15Hz frame rate into HD image data at a 60Hz frame rate for use in a digital TV system. As a result, the proposed system can reduce the processor performance to a level corresponding to an image display with a low frame rate, thereby reducing the product cost and allowing various additional functions. Finally, the proposed system is implemented to confirm effectiveness.

본 논문은 재료비의 절감을 위하여 저성능의 프로세서를 사용할 수 있도록 영상출력에 할당되는 프로세서 코어성능을 최대한 줄이고자 하는 것을 목적으로 한다. 본 논문은 저성능의 프로세서가 탑재된 전자앨범 기능의 모듈에 고해상도 영상출력 기능을 지원하기 위한 영상출력 시스템을 구현한다. 본 시스템은 영상데이터 처리부로부터의 15프레임의 HD 영상입력을 TV 시스템에서 사용 가능한 60프레임의 HD영상으로 출력하는 기능을 수행한다. 이 결과, 제안된 시스템은 프로세서 성능을 저프레임 영상출력에 해당하는 정도로 줄여줄 수 있으므로 이는 시스템의 비용 절감 및 다양한 부가기능 추가로 연결 되어진다. 결론적으로, 영상출력 시스템을 이용한 전자앨범 기능의 모듈 시스템을 개발하여 본 방식의 유효성을 확인한다.

Keywords

References

  1. 김익환, 최재승, '디지털 TV에 멀티미디어 부가기능을 구현하기 위한 시스템 설계 및 구현',2003년도 대한전자공학회 신호처리소사이어티 추계학술대회논문집, pp. 513-516, 2003
  2. Standard, 'High Definition TV Analog Component Video Interface', Electronic Industries Alliance (EIA), EIA-770.3, pp. 1-18, Sep. 1998
  3. T. Fujio, 'High Definition Television Systems: Desirable Standards, Signal Forms, and Transmission Systems', IEEE Trans. on Comm., Vol. 29, No. 12, pp. 1882-1891, 1981 https://doi.org/10.1109/TCOM.1981.1094954
  4. Datasheet, 'Information Technology Digital Compression and Coding of Continuous-Tone Still Images-Requirements and Guidelines', ITU, CCITT Rec. T.81, 1992
  5. L. Keun-Sup, P. Young Cheol, Y. Dae Hee, 'Software optimization of the MPEG-audio decoder using a 32-bit MCU RISC processor', IEEE Trans. on Consumer Electronics, Vol. 48, No.3, pp. 671-676, 2002 https://doi.org/10.1109/TCE.2002.1037059
  6. L. Wonchul, Y. Kisun, S. Wonyong, 'Software optimization of MPEG audio layer-III for a 32 bit RISC processor', Asia-Pacific Conference on Circuits and Systems, Vol. 1, pp. 435-438, 2002 https://doi.org/10.1109/APCCAS.2002.1114990
  7. Datasheet, 'High Performance Digital Image and Video Processor AT76C120', Atmel, 2004
  8. Datasheet, 'CF+ and CompactFlash Specification Revision 2.0', CompactFlash Association, 2003
  9. Datasheet, 'The MultiMediaCard System Summary Version 3.3', MMCA Technical Committee, March 2003
  10. Memory Stick Developers' site, 'http://www.memorystick.org/eng/e-index.html'
  11. C. Hoseok, L. Wonchul, S. Wonyong, 'Optimization of power consumption for an ARM7-based multimedia handheld device', Proceedings of the International Symposium on Circuits and Systems, Vol. 5, pp. 105-108, 2003 https://doi.org/10.1109/ISCAS.2003.1206199
  12. J. Geun-young, P. Ju-sung, 'Design of 32-bit RISC processor and efficient verification', Proceedings of the 7th Korea-Russia International Symposium on Science and Technology, Vol. 2, pp. 222-227, July 2003 https://doi.org/10.1109/KORUS.2003.1222609
  13. Datasheet, 'Sprtan-3 FPGA family: complete datasheet', Xilinx, pp. 1-193, Mar. 2004
  14. W. Chua-Chin, H. Ya-Hsin, C. Chiuan-Shian, H. Jih-Fon, 'A low-cost plasma display panel data dispatcher for image enhancement', IEEE Trans. on Consumer Electronics, Vol. 48, No.4, pp. 997-1003, Nov. 2002 https://doi.org/10.1109/TCE.2003.1196431