• Journal of information and communication convergence engineering
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• 제6권2호
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• 대한전기학회논문지:시스템및제어부문D
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• 제54권12호
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• pp.723-731
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• 2005

The $4{\times}4$ homogeneous transformation matrix is a compact representation of orientation and position of an object in robotics and computer graphics. A coordinate transformation is accomplished through the successive multiplications of homogeneous matrices, each of which represents the orientation and position of each corresponding link. Thus, for real time control applications in robotics or animation in computer graphics, the fast multiplication of homogeneous matrices is quite demanding. In this paper, a parallel-architecture vector processor is designed for this purpose. The processor has several key features. For the accuracy of computation for real application, the operands of the processors are floating point numbers based on the IEEE Standard 754. For the parallelism and reduction of hardware redundancy, the processor takes column vectors of homogeneous matrices as multiplication unit. To further improve the throughput, the processor structure and its control is based on a pipe-lined structure. Since the designed processor can be used as a special purpose coprocessor in robotics and computer graphics, additionally to special matrix/matrix or matrix/vector multiplication, several other useful instructions for various transformation algorithms are included for wide application of the new design. The suggested instruction set will serve as standard in future processor design for Robotics and Computer Graphics. The design is verified using FPGA implementation. Also a comparative performance improvement of the proposed design is studied compared to a uni-processor approach for possibilities of its real time application.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.380-382
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• 2001

This paper presents the implementation of IEEE 802.11 Medium Access Control and Physical Layer Protocol that can be applied to wireless LAN system. We have used PRISM2 chipsets from Intersil to build the baseband, IF, and RF parts. DSSS(Direct Sequence Spread Spectrum) physical layer at 2.4GHz ISM band is adopted in the hardware prototype. To meet the high-speed requirement of physical layer, we have designed the MAC protocol layer with embedded firmware and FPGA. The prototype board is shown to be able to support the physical layer of 5GHz and 600Hz wireless LAN systems.

• 전기전자학회논문지
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• 제2권2호
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• pp.225-232
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• 1998

Currently NTSC, PAL, and SECOM are widely used for TV broadcasting systems. In Korea, NTSC has been used to reduce transmission bandwidth and broadband flickers using the Interlaced scanning method. Image data in the Interlaced scanning method require De-interlacing compensation for PC-based multimedia applications. The existing compensation algorithms such as ZOI, FOI, and ELA provieds simple computations and effective image compensation while the PSNR is low and horizontal and vertical edges are hardly detected. In this paper, the ADI(Adaptive De-Interlacing) algorithm that can increase PSNR and detect horizontal and vertical edges is proposed and a hardware system is implemented using three ACTEL 1020B FPGA chips. The system consists of the algorithm part implemented using two FPGAs and the memory control part implemented using rest one. Also the system operation is investigated for real time processing.

• 센서학회지
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• 제29권1호
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• 전기전자학회논문지
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• 제18권4호
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• pp.495-501
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• 2014

본 논문에서는 IEEE 802.11p WAVE 모뎀을 위한 다이버시티 모뎀 구조를 제안하고 설계하였으며, 이를 실차에 장착하여 성능테스트를 수행하였다. 제안한 구조는 듀얼채널과 다이버시티 기능을 선택적으로 수행할 수 있으며, 선택적 안테나 다이버시티와 Maximum Ratio Combining (MRC) 다이버시티 기능 중하나를 선택하여 수신할 수 있다. 개발된 구조는 HDL로 설계되어 Xillinx Kintex7보드를 이용하여 실도로에서 실차에 장착하여 테스트를 수행하여 성능을 검증하였다. 실험결과 개발된 다이버시티 모뎀은 단일 채널 모뎀에 비하여 안정적인 통신 성공률을 유지할 수 있으며, 전송거리도 30%이상 향상됨을 확인하였다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.289-291
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• 2007

The Digital Multimedia Broadcasting(DMB) system is developed to offer high quality audio-visual multimedia contents to the uses by the various portable terminals in the mobile environment. Integrated complex reception platform is required to receive multimedia broadcasting services transmitted from various transmission media. In this paper, we present the design and implementation technic for providing the both of terrestrial and satellite DMB services simultaneously using the same hardware platform. The implemented complex receiving terminal to accommodate these DMB services simultaneously need composed of it RF module. it baseband module, it complex control module and the complex de-multiplexer module. The complex control module is designed using uClinux operating system. The complex de-multiplexer, which perform the functions of the address decoder and each DMB stream de-multiplexer, is implemented. with FPGA device. The implemented platform is tested in a real environment and its performance is satisfied with required performance criteria.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2006년도 한국컴퓨터종합학술대회 논문집 Vol.33 No.1 (A)
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• pp.226-228
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• 2006

In this paper we describe a simulation and development framework for designing mobile 3D graphics architectures. We are developing a simple and flexible simulation and verification environment (SVE) that uses gITrace's ability to intercept and redirect an OpenGL/ES streams. In combination wlth gITrace to trace OpenGL/ES commands, the SVE simulates the behavior of mobile 3D graphics pipeline during playback of traces, and then produces the second geometry trace that can be used as a test vector for the Verilog/HDL RT-level model. By comparing the frame-by-frame results, we can conduct architectural verification. To demonstrate the functionality of the SVE, we show the implementation of the verified mobile 3D architecture on a FPGA board. For this, we also present an application development environment (ADE) includes a mobile graphics API and a device driver interface (DDI). The proposed two software environments, the SVE and the ADE could be used fer developing and testing mobile applications, architectural study and speculative hardware designs.

• 대한의용생체공학회:학술대회논문집
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• 대한의용생체공학회 1998년도 추계학술대회
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• pp.299-300
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• 1998

Recently the development of medical modality like as MRI, 3D US, DR etc is very active. Therefore it is more required not only the enhancement of quality in medical service but the improvement of medical system based on quantization, minimization, and optimization of high speed. Especially, as the changing into the digital modality system, it gets to start using ASIC(Application Specific Integrated Circuit) to realize one board system. It requires the implementation of hardware debugging and effective speedy algorithm with more speed and accuracy in order to support and replace existing device. If objected image could be linked to high speed process board with special interface and pre-processed using FPGA, it can be used in real time image processing and protocol of HIS(Hospital Information System). This study can support the basic circuit design of medical image board which is able to realize image processing basically using digitalized medical image, and to interface between existing device and image board containing image processing algorithm.

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2001년도 하계 학술대회 논문집(KISPS SUMMER CONFERENCE 2001
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• pp.101-104
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• 2001

본 논문에서는 5GHz 대역을 사용하는 무선 LAN의 표준안인 IEEE 802.11a-1999를 위한 디지털 자동 이득 제어기를 제안한다. 송수신간의 동기화를 위한 신호인 Training symbol을 이용하여 수신기에 입력되는 신호의 이득을 측정한다. 측정된 이득을 이상적인 이득과 비교하여 갱신할 이득을 구한다. 갱신 이득은 신호를 증폭하는GCA(Gain Controlled Amplifier)의 입력 전압으로 변환되어 신호의 증폭도를 제어하게 된다. 본 논문에서는 하드웨어 부담을 줄이기 위해 부분 선형 근사방법을 이용하여, 갱신 이득을 GCA의 입력 전압으로 변환한다. 보다 정확한 제어를 위하여 이득 측정 및 제어 값의 갱신을 7회 반복하여 수행한다. 본 논문에서 제안한 디지털 자동 이득 제어기는 VHDL을 이용하여 설계하였으며, Xilinx CAD Tool을 이용하여 Timing Verification을 수행하였다.