• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.10a
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• pp.477-479
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• 2017

With the recent advances in medical technology and health care, the prevention and treatment of diseases has developed. Accordingly aging has rapidly progressed. In this life span and aging society, demand for diagnostic centered medical care is increasing rapidly. In this paper, we propose a wearable patient check system based on FPGA that can be controlled by sensors. In the existing hospital, a doctor or nurse visited the patient every hour to check the condition. However, in this paper, patients, doctors and nurses can check the patient's condition at the desired time using patient check system. In addition, the tilt sensor is used for the patient who is uncomfortable to easily control. The proposed FPGA-based hardware architecture consists of an algorithm for enlarged image processing, a TFT-LCD Controller, a CIS Controller, and a Memory Controller to output the patient's status image. Implemented and validated using the DE2-115 test board with Cyclone IV EP4CE115F29C7 FPGA device and its operating frequency is 50MHz.

• Journal of IKEEE
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• v.27 no.4
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• pp.601-609
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• 2023

In this paper, we propose an artificial intelligence-based high-speed fault diagnosis method using an FPGA in the event of a ground fault in a DC system. When applying artificial intelligence algorithms to fault diagnosis, a substantial amount of computation and real-time data processing are required. By employing an FPGA with AI-based high-speed fault diagnosis, the DC breaker can operate more rapidly, thereby reducing the breaking capacity of the DC breaker. therefore, in this paper, an intelligent high-speed diagnosis algorithm was implemented by collecting fault data through fault simulation of a DC system using Matlab/Simulink. Subsequently, the proposed intelligent high-speed fault diagnosis algorithm was applied to the FPGA, and performance verification was conducted.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.10
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• pp.17-28
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• 1999

In this paper, an ASIC emulation system called ACE (ASIC Emulator) is proposed. It can produce the prototype of target ASIC in a short time and verify the function of ASIC circuit immediately The ACE is consist of emulation software in which there are EDIF reader, library translator, technology mapper, circuit partitioner and LDF generator and emulation hardware including emulation board and logic analyzer. Technology mapping is consist of three steps such as circuit partitioning and extraction of logic function, minimization of logic function and grouping of logic function. During those procedures, the number of basic logic blocks and maximum levels are minimized by making the output to be assigned in a same block sharing product-terms and input variables as much as possible. Circuit partitioner obtain chip-level netlists satisfying some constraints on routing structure of emulation board as well as the architecture of FPGA chip. A new partitioning algorithm whose objective function is the minimization of the number of interconnections among FPGA chips and among group of FPGA chips is proposed. The routing structure of emulation board take the advantage of complete graph and partial crossbar structure in order to minimize the interconnection delay between FPGA chips regardless of circuit size. logic analyzer display the waveform of probing signal on PC monitor that is designated by user. In order to evaluate the performance of the proposed emulation system, video Quad-splitter, one of the commercial ASIC, is implemented on the emulation board. Experimental results show that it is operated in the real time of 14.3MHz and functioned perfectly.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.05a
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• pp.407-409
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• 2015

In this paper, a hardware implementation of MOD(Moving Object Detection) algorithm is described, which is based GMM(Gaussian Mixture Model) and background subtraction. The EGML(Effective Gaussian Mixture Learning) is used to model and update background. Some approximations of EGML calculations are applied to reduce hardware complexity, and pipelining technique is used to improve operating speed. Gaussian parameters are adjustable according to various environment conditions to achieve better MOD performance. MOD processor is verified by using FPGA-in-the-loop verification, and it can operate with 109 MHz clock frequency on XC5VSX95T FPGA device.

• Journal of IKEEE
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• v.22 no.3
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• pp.700-705
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• 2018

In this paper, we propose the gas classifier based on restricted column energy neural network (RCE-NN) and present its hardware implementation results for real-time learning and classification. Since RCE-NN has a flexible network architecture with real-time learning process, it is suitable for gas classification applications. The proposed gas classifier showed 99.2% classification accuracy for the UCI gas dataset and was implemented with 26,702 logic elements with Intel-Altera cyclone IV FPGA. In addition, it was verified with FPGA test system at an operating frequency of 63MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.279-282
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• 2012

In this paper, a hardware architecture of phase calculator for 3D image processing is proposed. The designed phase calculator, which adopts a pipelined architecture to improve throughput, performs arctangent operation using vectoring mode of CORDIC algorithm. Fixed-point MATLAB modeling and simulations are carried out to determine the optimized bit-widths and number of iteration. Phase calculator designed in Verilog HDL is verified by emulating the restoration of virtual 3D data using MATLAB/Simulink and FPGA-in-the-loop verification.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.719-721
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• 2013

A thinning stage of fingerprint algorithm occupies 39% cycle of microprocessor system for identification processing of image from fingerprint sensor. Hardware block processing is more effective than software one in speed and power consumption, because a thinning algorithm is iteration of simple instructions without a transcendental function. This paper describes an effective hardware scheme for thinning stage processing using Verilog-HDL in $64{\times}64$ Pixel Array. The hardware scheme is designed and simulated in RTL. The logic is also synthesized by XST in FPGA environment and tested. Experimental results show the performance of the proposed scheme and possibility of application for a soft microprocessor and thinning processor embedded fingerprint SoC.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.5
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• pp.906-914
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• 2007

In the upstream link of EPON, numerous ONUs In the reverse link of the EPON network, numerous ONUs receive the privileges to use the optical medium from the scheduler of the LOT, but not through the competition with others. Therefore, it is very important to select a proper DBA algorithm to allocatethe frequency band to each ONU in an effectively and fair manner. In our preceding study, we proposed the RC-DBA algorithm that complements many problems in existing DBA algorithms. In this paper, we designed the MAC scheduler for the OLT, which the proposed algorithmwas applied to and implement it in the FPGA. In addition, in order to verify the operation of the scheduler, we developed the embedded Linux based testbed.

• Journal of IKEEE
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• v.18 no.3
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• pp.305-312
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• 2014

IIt takes a lot of time and needs the workloads to verify the RTL code used in complex system like a nuclear control system which is required high level reliability using simple testbench. UVM has a layered testbench architecture and it is easy to modify the testbench to improve the code coverage. A test vector can be easily constructed in the UVM, since a constrained random test vector can be used even though the construction of testbench using UVM. We showed that the UVM testbench is easier than the verilog testbench for the analysis and improvement of code coverage.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.23 no.9
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• pp.124-129
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• 2009

Recently, PWM inverter is widely utilized for many industrial applications such as high performance drive and space vector pulse width modulation(SVPWM) inverter which has high voltage ratio and low harmonics compared to conventional PWM inverter. This paper presents the implementation on a field programmable gate array(FPGA) of a SVPWM module for a voltage source inverter. The SVPWM module consists of PWM generator, current and position sensor interface and dead time compensator. The implemented SVPWM module can be integrated with a digital signal processor(DSP) to provide a flexible and effective solution for high performance voltage source inverter and for the use of multi-motor control. The performance of SVPWM module is verified by simulation and several experimental results.