• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.273-273
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• 2011

현재 사용되고 있는 플로팅 게이트를 이용한 플래시 메모리 소자는 비례축소에 의해 발생하는 단 채널 효과, 펀치스루 효과 및 소자간 커플링 현상과 같은 문제로 소자의 크기를 줄이는데 한계가 있다. 이러한 문제를 해결하기 위하여 silicon nitride와 같은 절연체를 전자의 트랩층으로 사용하는 charge trap flash (CTF) 메모리 소자에 대한 연구가 활발히 진행되고 있다. CTF 메모리 소자의 전기적 특성에 대한 연구는 활발히 진행 되었지만, 수치 해석 모델을 사용하여 메모리 소자의 전하수송 메커니즘을 분석한 연구는 매우 적다. 본 연구에서는 수치 해석 모델을 적용하여 개발한 시뮬레이터를 사용하여 CTF 메모리 소자의 프로그램 동작 시 전하수송 메커니즘에 대한 연구를 하였다. 시뮬레이터에 사용된 모델은 연속방정식, 포아송 방정식과 Shockley-Read-Hall 재결합 모델을 수치해석적 방법으로 계산하였다. 또한 CTF 소자 프로그램 동작 시 트랩 층으로 주입되는 전자의 양은 Wentzel-Kramers-Brillouin 근사 법을 이용하여 계산하였다. 트랩 층에 트랩 되었던 전자의 방출 모델은 이온화 과정을 사용하였다. 게이트와 트랩 층 사이의 터널링은 Fowler-Nordheim (FN) tunneling 모델, Direct tunneling 모델, Modified FN tunneling 모델을 적용하였다. FN tunneling 만을 적용했을때 보다 세가지 모델을 적용했을 때가 더 실험치와의 오차가 적었다. 그 이유는 시뮬레이션 결과를 통해 인가된 전계에 의해 Bottom Oxide 층의 에너지 밴드 구조가 변화하여 세가지 tunneling 모델의 구역이 발생하는 것을 확인 할 수 있었다. 계산된 결과의 전류-전압 곡선을 통해 CTF 메모리 소자의 프로그램 동작 특성을 관찰하였다. 트랩 층의 전도대역과 트랩 층 내부에 분포하는 전자의 양을 시간에 따라 계산하여 트랩 밀도가 시간이 지남에 따라 일정 값에 수렴하고 많은 전하가 트랩 될 수록 전하 주입이 줄어듬을 관찰 하였다. 이와 같은 시뮬레이션 결과를 통해 CTF 메모리의 트랩층에서 전하의 이동에 대해 더 많이 이해하여 CTF 소자가 가진 문제점 해결에 도움을 줄 것이다.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.53-63
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• 1993

Device degradations by the Fowler-Nordheim tunneling have been studide. The changes of device characteristics such as the threshold voltage, subthreshold slope, I-.or. curves have been measured after bidirectionally stressing n-channel MOSFET's and p-channel MOSFET's. Also the interface states have been directly measured by the charge pumping methodIt is shown that the change of interface states is determined by the number of hole carriers tunneling the gate oxide and electrons which are trapped in the gate oxide. Also, in this paper, we propose a model for device lifetime limited by the increase of interface states.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.11a
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• pp.800-803
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• 2002

The MONOS capacitor are fabricated to investigate the carrier trapping due to Fowler-Nordheim tunneling injection. The carrier trapping in scaled multi-dielectric(ONO) depends on the nitride and Op oxide thickness under Fowler_Nordheim tunneling injection. Carriers captured at nitride film could not escape from nitride to gate, but be captured at top oxide and nitride interface traps because of barrier height of top oxide. Therefore, it is expected that the MONOS memory devices using multi dielectric films enhance memory effect and have a long memory retention characteristic.

• Journal of KIISE:Information Networking
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• v.30 no.3
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• pp.343-354
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• 2003

This paper describes algorithm that minimizes recovery time of packet loss resulting from handoff in multicast environments and guarantees reliability through interaction of FN(Foreign Network) with PMTP(Predictable Multicast Tree Protocol). To solve the problems that inefficient routing and handoff delay taking plate when using hi-directional tunneling and remote subscription independently in multicast environments, proposed algorithm uses tunneling and rejoining multicast group according to the status of an arriving FA in a foreign network. Furthermore, proposed algorithm sends packet loss information and register message to previous FA or current FA at the same time. so, MH is able to recovery packet loss in handoff delay as soon as possible. As a result of performance analysis, proposed algorithm is more efficient than previous researches and is applicable to existing handoff method without requiring additional procedures.

• KIPS Transactions on Computer and Communication Systems
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• v.5 no.1
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• pp.1-6
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• 2016

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.240-240
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• 2010

A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (${\sim}\;1.2{\times}10^{13}/cm^2$) was fabricated. Its structural effect for multiple layers was evaluated and compared to one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with 2-4 multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler-Nordheim (FN)-tunneling could be a candidate structure for future flash memory.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.21-25
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• 2006

To improve the performance of organic thin film transistor, we investigated the properties of gate insulator's surface according to the leakage current by I-V measurement. The surface was treated by the dilute n-octadecyltrichlorosilane solution. The alkyl group of n-octadecyltrichlorosilane induced the electron tunneling and the electron tunneling current caused the breakdown at high electric field, consequently shifting the breakdown voltage. The 0.5% sample with an electron-rich group was found to have a large leakage current and a low barrier height because of the effect of an energy barrier lowered by, thermionic current, which is called the Schottky contact. The surface properties of the insulator were analyzed by I-V measurement using the effect of Poole-Frankel emission.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.852-855
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• 2012

A DC-DC converter for EEPROM IPs which perfom erasing by the FN (Fowler-Nordheim) tunneling and programming by the band-to-band tunneling is designed in this paper. For the DC-DC converter for EEPROM IPs using a low voltage of $1.5V{\pm}10%$ as the logic voltage, a scheme of using VRD (Read Voltage) instead of VDD is proposed to reduce the pumping stages and pumping capacitances of its charge pump circuit. VRD ($=3.1V{\pm}0.1V$) is a regulated voltage by a voltage regulator using an external voltage of 5V. The designed DC-DC converter outputs VPP (=8V) and VNN (=-8V) in the write mode.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.13 no.1
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• pp.48-57
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• 2020

MCU used in applications such as wireless chargers and USB type-C require MTP memory with a small cell size and a small additional process mask. Conventional double poly EEPROM cells are small in size, but additional processing masks of about 3 to 5 sheets are required, and FN tunneling type single poly EEPROM cells have a large cell size. In this paper, a 110nm MTP cell using a vertical PIP capacitor is proposed. The erase operation of the proposed MTP cell uses FN tunneling between FG and EG, and the program operation uses CHEI injection method, which reduces the MTP cell size to 1.09㎛2 by sharing the PW of the MTP cell array. Meanwhile, MTP memory IP required for applications such as USB type-C needs to operate over a wide voltage range of 2.5V to 5.5V. However, the pumping current of the VPP charge pump is the lowest when the VCC voltage is the minimum 2.5V, while the ripple voltage is large when the VCC voltage is 5.5V. Therefore, in this paper, the VPP ripple voltage is reduced to within 0.19V through SPICE simulation because the pumping current is suppressed to 474.6㎂ even when VCC is increased by controlling the number of charge pumps turned on by using the VCC detector circuit.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.