• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.568-576
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• 2017

This paper presents a clock and data recovery circuit with an adaptive loop bandwidth calibration scheme and the idle power saved frequency acquisition. The loop bandwidth calibration adaptively controls injection currents of the main loop with a trimmable bandgap reference circuit and trains the VCO to operate in the linear frequency control range. For stand-by power reduction of the phase detector, a clock gating circuit blocks 8-phase clock signals from the VCO and cuts off the current paths of current mode D-flip flops and latches during the frequency acquisition. 77.96% reduction has been accomplished in idle power consumption of the phase detector. In the jitter experiment, the proposed scheme reduces the jitter tolerance variation from 0.45-UI to 0.2-UI at 1-MHz as compared with the conventional circuit.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.47-53
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• 2004

We present the design of ternary flip-flop which is based on ternary logic so as to process ternary data. These flip-flops are composed with ternary voltage mode NMAX, NMIN, INVERTER gates. These logic gate circuits are designed using CMOS and obtained the characteristics of a lower voltage, lower power consumption as compared to other gates. These circuits have been simulated with the electrical parameters of a standard 0.35um CMOS technology and 3.3Volts supply voltage. The architecture of proposed ternary flip-flop is highly modular and well suited for VLSI implementation, only using ternary gates.

• Proceedings of the KIEE Conference
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• 2004.07d
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• pp.2685-2686
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• 2004

심자도(Magnetocardiography: MCG)는 심장에서 발생하는 자기신호로 크기가 수 pico Tesla에서 수 femto Tesla 정도로 지구 자기에 비하여 $10^{-6}{\sim}10^{-10}$ 정도로 매우 작기 때문에 보통 3층의 차폐 막 구조로 되어 있는 자기차폐실을 사용하여 외부 잡음을 줄인다. 그러나 자기차폐실의 비용이 크기 때문에, 자기차폐실의 비용을 줄이고 다양한 신호처리를 병행하여 신호대 잡음비를 높이고 있다. 본 논문에서는 1Giga FLOPS (FLoating point Operationals Per Second)의 부동 소숫점 연산능력을 가진 TMS320C6701을 사용하여 실시간 신호처리가 가능한 신호처리 시스템을 설계하였다. 개발된 DSP 보드는 PCI-bus 기반으로 설계하여 신호 측정 컴퓨터에 내장이 가능하도록 하였다. 프로그램과 데이터 처리를 위한 외부 메모리를 장착하였고, PCI 콘트롤러를 갖추어 PC 와의 대용량 메모리 공유가 가능하도록 하였다. 제작된 DSP 보드를 사용하여, 심자도 신호에서 실시간으로 적응 잡음 소거 및 필터링을 구현하여 신호대 잡음비의 향상을 확인할 수 있었다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.1
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• pp.11-22
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• 2016

Clock skew scheduling is one of the essential steps to be carefully performed during the design process. This work addresses the clock skew optimization problem integrated with the consideration of the inter-dependent relation between the setup and hold times, and clock to-Q delay of flip-flops, so that the time margin is more accurately and reliably set aside over that of the previous methods, which have never taken the integrated problem into account. Precisely, based on an accurate flexible model of setup time, hold time, and clock-to-Q delay, we propose a stepwise clock skew scheduling technique in which at each iteration, the worst slack of setup and hold times is systematically and incrementally relaxed to maximally extend the time margin. The effectiveness of the proposed method is shown through experiments with benchmark circuits, demonstrating that our method relaxes the worst slack of circuits, so that the clock period ($T_{clk}$) is shortened by 4.2% on average, namely the clock speed is improved from 369 MHz~2.23 GHz to 385 MHz~2.33 GHz with no time violation. In addition, it reduces the total numbers of setup and hold time violations by 27.7%, 9.5%, and 6.7% when the clock periods are set to 95%, 90%, and 85% of the value of Tclk, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.67-73
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• 2000

The state assignment for a finite state machine greatly affects the delay, area, and testabilities of the sequential circuits. In order to minimize the dependencies among groups of state variables, therefore possibly to reduce the length and number of feedback cycles, a new state assignment technique based on m-block partition is introduced in this paper. After the completion of proposed state assignment and logic synthesis, partial scan design is performed to choose minimal number of scan flip-flops. Experiment shows drastic improvement in testabilities while preserving low area and delay overhead.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.443-450
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• 2013

This paper propose a new ROM data encoding method that takes into account of a sequential access pattern to reduce the power consumption in ROMs used in applications such as FIR filters that access the ROM sequentially. In the proposed encoding method, the number of 1's, of which the increment leads to the increase of the power consumption, is reduced by applying an exclusive-or (XOR) operation to a bit pair composed of two consecutive bits in a bit line. The encoded data can be decoded by using XOR gates and D flip-flops, which are usually used in digital systems for synchronization and glitch suppression. By applying the proposed encoding method to coefficient ROMs of FIR filters designed by using various design methods, we can achieve average reduction of 43.7% over the unencoded original data in the power consumption, which is larger reduction than those achieved by previous methods.

• Korean Journal of Applied Biomechanics
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• v.21 no.1
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• pp.9-16
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• 2011

The purpose of this study is to analyze the effects of both various shoe types and bare feet on ground reaction force while walking. Ten first-year female university students were selected. A force platform(Kistler, Germany) was used to measure ground reaction force. Six types of shoe were tested: flip flops, canvas shoes, running shoes, elevated forefoot walking shoes, elevated midfoot walking shoes, and five-toed shoes. The control group was barefooted. Only vertical passive/active ground reaction force variables were analyzed. The statistical analysis was carried out using the SAS 9.1.2 package, specifically ANOVA, and Tukey for the post hoc. The five-toed shoe had the highest maximum passive force value; while the running shoe had the lowest. The first active loading rate for running shoes was the highest; meanwhile, bare feet, the five-toed shoe, and the elevated fore foot walking shoe was the lowest. Although barefoot movement or movement in five toed shoes increases impact, it also allows for full movement of the foot. This in turn allows the foot arch to work properly, fully flexing along three arches(transverse, lateral, medial), facilitating braking force and initiating forward movement as the tendons, ligaments, and muscles of the arch flex back into shape. In contrast movement in padded shoes have a tendency to pound their feet into the ground. This pounding action can result in greater foot instability, which would account for the higher loading rates for the first active peak for padded shoes.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.140-151
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• 1996

In this study, we designed the routing structure and logic block of a SRAM cell-based FPGA with symmetrical-array architecture. The designed routing structure is composed of switch matrices, routing channels and I/O blocks, and the routing channels can be subdivided into single length channels, double length channels and global length channels. The interconnection between wires is made through SRAM cell-controlled pass transistors. To reduce the signal delay in pass transistors, we proposed a scheme raising the gate-control voltage to 7V. The designed SRAM cells have built-in shift register capability, so there is no need for separate shift registers. We designed SRAM cells in the LUTs(look-up tables) to enable the wirte operations to be performed synchronously with the clock for ease of system application. Each logic block (LFU) has four 4-input LUTs, flip-flops and other gates, and the LUTs can be used a sSRAM memory. The LFU also has a dedicated carry logic, so a 4-bit adder can be implemented in one LFU. We designed our FPGA using 0.6.mu.m CMOS technology, and simulation shows proper operation of a 4 bit counter at 100MHz.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.1
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• pp.79-86
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• 1996

In this paper we propose an architecture for VLC(Variable Length Coder) and VLD(Variable Length Decoder) which is simple with respect to implementation point and efficient in memory. We implemented encoding and decoding circuit where we need only 7-bit address memory space for 114 MPEG1 DCT coefficients and employed minimal number of flip-flops and logics for an architecture to integrate a shift register for serial-to-parallel or parallel-to-serial conversion of the data in code mapping ROM. We obtained 50Mbps operating speed in both encoding and decoding process as the result of simulation using 0.80.8${\mu}m$ CMOS standard cells.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.168-176
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• 2015

Due to the reduction in device feature size, transient faults (soft errors) in logic circuits induced by radiations increase dramatically. Many researches have been done in modeling and analyzing the susceptibility of sequential circuit elements caused by soft errors. However, to the best knowledge of the authors, there is no work which has well considerated the feedback characteristics and the multiple clock cycles of sequential circuits. In this paper, we present a new method for evaluating the susceptibility of sequential circuit elements to soft errors. The proposed method uses four Error Propagation Probability Matrixs (EPPMs) to represent the error propagation probability of logic gates and flip-flops in current clock cycle. Based on the predefined matrix union operations, the susceptibility of circuit elements in multiple clock cycles can be evaluated. Experimental results on ISCAS'89 benchmark circuits show that our method is more accurate and efficient than previous methods.