• 방송공학회논문지
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• 제16권4호
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• pp.624-634
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• 2011

최근 차세대 비디오 코딩 표준화를 위해 JCT-VC에서 HEVC라 불리는 새로운 비디오 압축 표준 기술을 개발하고 있다. HEVC는 H.264/AVC보다 높은 성능을 갖는 많은 부호화 기술을 채택하였다. 그중 색차 신호를 보간할 때 H.264/AVC에서 사용된 선형필터보다 좋은 성능을 가지는 DCT 기반으로 한 보간 필터를 사용하고 있다. 본 논문에서는 H.264/AVC에서 사용된 FIR필터와 선형필터를 통합한 필터를 제안하여 부호화 효율을 높이는 방법을 제안한다. 제안하는 방법과 DCT 기반으로 한 보간 필터와 비교하였을 때 실험결과로 제안한 방법은 random access구조의 high efficiency 경우 색차성분 U,V에서 각각 평균 0.9%, 1.1%의 BD-rate가 감소하였고,random access의 low complexity 구조인 경우 색차성분 U,V에서 각각 평균 1.1%, 1.1%의 BD-rate가 감소하였고, low delay의 high efficiency 구조인 경우 색차성분 U,V에서 각각 평균 0.9%, 1.4%의 BD-rate가 감소하였고, low delay 구조의 low complexity인 경우 색차성분 U,V에서 각각 평균 1.8%, 1.8%의 BD-rate가 감소하였다.

• 대한전자공학회논문지
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• 제22권3호
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• pp.16-22
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• 1985

In this paper a new algorithm named modified delta modulation (MDM) for encoding filter coefficients is proposed. And this paper presents the designing method of multiplier less FIR filters rosin영 Proposed MDM a19orithm. In the delta modulation (DM) system the quantiaation levels consist of two levels $\pm$1, but in newly proposed MDM algorithm quantization levels are extended to many levels 0, $\pm$2$^n$, n=0, 1, 2... It is recognized by the result of computer simulations that frequency response of multi-plierless FIR filters designed by MDM algorithm is relatively good. And comparing with con-ventional FIR filters on the number of hardware devices, this filter needs a little increased memory, but regardless of filter order it needs only one multiplier which is used for signal scaling.

• 전자공학회논문지B
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• 제30B권5호
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• pp.18-26
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• 1993

This paper presents the design method for two-dimensional FIR digital filter using optimization scheme. The proposed design method is to extend the optimal one-dimensional filter design algorithm proposed by Parks and McClellan to two-dimensional case. When extending one-dimensional design scheme to two-dimensional one, some problems occur. In this paper we solved the problems by using the least square error model, the two-dimensional Lagrange interpolation, and the modified alternation theory. As a result, the equi-ripple FIR filter is obtained that is more optimal and more specific than the conventional methods.

• 전자공학회논문지B
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• 제30B권5호
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• pp.27-33
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• 1993

This paper describes the hardware implementation of 2-D FIR digital filter for a real-time image processing. Generally, the most time-consuming operation in signal processing is the multiplication operation. To avoid it in digital filter. Pelid and Liu proposed the distributed arithmetic method for the one-dimensional case. The implementation method proposed in this paper is to extend Pelid's method to two-dimensional FIR filter using simple ROM lookup table and to use the technique of pipe lining two main operations of memory access and arithmetic. As a result, the speed of our proposed hardware implementation is two times faster than that of conventional methods and can be close to the real time speed.

• ETRI Journal
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• 제33권5호
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• pp.695-703
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• 2011

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

• 대한의용생체공학회:의공학회지
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• 제10권2호
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• pp.83-88
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• 1989

This paper is a study on the design of adptive filter for QRS complex detection. We propose a simple adaptive algorithm to increase capability of noise cancelation in QRS complex detection with two stage adaptive filter. At the first stage, background noise is removed and at the next stage, only spectrum of QRS complex components is passed. Two adaptive filters can afford to keep track of the changes of both noise and QRS complex. Each adaptive filter consists of prediction error filter and FIR filter The impulse response of FIR filter uses coefficients of prediction error filter. The detection rates for 105 and 108 of MIT/BIH data base were 99.3% and 97.4% respectively.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2005년도 ICCAS
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• pp.2532-2537
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• 2005

FIR(Finite Impulse Response) filter is well known to be ideal for the finite time state-space model, but it requires much computation due to its inherent non-recursive structure especially when the measurement interval grows to a large extent. And often a fixed-lag smoother based on the finite time interval is needed to monitor the soundness of the system model and the measurement model, but the computation burden of FIR-type smoother imposes much restriction of its usage for real-time application. Conventional recursive forms of FIR estimator[1]-[4] could not be used for real time applications, since they are numerically unstable in their recursive equations. To cope with this problem, we suggest a stable recursive form FIR estimator(SRFIR) and its usefulness is demonstrated for designing the real-time fixed-lag smoother on the finite time window through an example of detection of rate bias in the anti-aircraft gun fire control system.

• 대한전자공학회논문지SP
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• 제47권1호
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• pp.150-158
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• 2010

디지털 신호의 표본화 속도를 변환시키는 SRC(sample rate converter) 장치에는 필터가 필요하다. 속도 변환율이 높을수록 필터의 신호처리량이 증대되며, 필터의 구현이 복잡해진다. 그러므로 속도 변환율이 높은 경우에는 신호처리량이 적은 필터를 설계하는 것은 중요한 문제이다. 본 논문에서는 다단 FIR(finite impulse response) 필터를 효과적으로 설계하는 방법을 제시하였다. 다단 필터는 표본화 속도를 한 번에 변환하는 것이 아니라 여러 단 나누어서 변환하는 방식이다. 제시된 설계방식은, 속도 변환율의 인수분해 조합 모두에 대하여 조사하며, 필터의 복잡도 측정을 필터 차수의 추정식에 의존하지 않고 필터의 구현 결과를 바탕으로 한 점이 특징이다. 필터 설계 결과, 종래의 방식으로 설계된 것보다 곱셈연산량이 적음을 보였다. 또한 halfband 필터나 다중 차단대역 필터 등의 특성을 활용하면 곱셈연산량이 더욱 감소된 필터를 구성할 수 있음을 확인하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1996년도 한국자동제어학술회의논문집(국내학술편); 포항공과대학교, 포항; 24-26 Oct. 1996
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• pp.980-983
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• 1996

A new version of the discrete-time optimal FIR (finite impulse response) filter utilizing only the measurements of finite sliding estimation window is suggested for linear time-invariant state-space models. This filter is called the BLUFIR (best linear unbiased finite impulse response) filter since it provides the BLUE (best linear unbiased estimate) of the state obtained from the measurements of the estimation window. It is shown that the BLUFIR filter has the deadbeat property when there are no noises in the estimation window.

• 전자공학회논문지
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• 제49권11호
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• pp.141-148
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• 2012

Oversampling 기법을 사용한 analog-to-digital (A/D) 컨버터에서 샘플링 된 신호의 signal bandwidth를 낮추어 주기 위해 데시메이션 필터가 사용된다. 본 논문은 sigma-delta ADC에 사용될 수 있는 저전력 4 단 32 bit 데시메이터 필터 디자인을 제안한다. 디지털 데시메이션 필터는 CIC(cascaded integrator-comb) filter와 세 개의 half-band FIR filter로 이루어져 있다. 전력소모를 최소화하기 위하여 CIC filter에는 pipeline구조가 사용되었고, FIR 필터의 multiplier 구조를 최적화하기 위하여 Canonic Signed Digit (CSD) 코드가 사용되었다. 130nm CMOS 공정으로 설계 자동화 CAD 도구를 사용하여 타이밍, 면적, 전력소모를 최적화하여 98.304 MHz 주파수에서 697 uW의 전력을 소모면서 32 bit, 192 kHz 아웃풋을 낼 수 있다.