• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.379-382
• /
• 2000

We designed a self-timed interface circuit for efficient communication in IP (Intellectual Property)-based system with high-speed self-timed FIFO and a set of self-timed event logic library with 0.25um CMOS technology. Optimized self-timed standard cell layouts and Verilog models are generated for top-down design methodology. A method for mitigating a design bottleneck when it comes to tolerate clock skew is described. With clock control method and FIFO, we implemented high-speed 32bit-interface chip for self-timed system, which generated maximum system clock is 2.2GHz. The size of the core is about 1.1mm x 1.1mm.

• Proceedings of the Korean Information Science Society Conference
• /
• 2001.04a
• /
• pp.130-132
• /
• 2001

현재 인터넷은 노력형 서비스(Best-effort service)만을 제공하며, 보장형 서비스(Guaranteed service)를 제공하지 못하는 한계를 가지고 있다. MPEG1, MPEG4, H.263과 같은 실시간 비디오 데이터를 효과적으로 제공하기 위해서는 보장형 서비스를 필요로 하며, 세션 관리, 호 허용 제어, 패킷 스케쥴링과 같은 여러 가지 기술들이 필요하다. 기존에 주로 사용되고 있는 FIFO(First-in First-out)에 의한 큐잉 정책으로는 대역폭, 지연 시간과 같은 네트워크 자원을 사용자에게 보장해 줄 수 없다. 따라서 CBQ(Class Based Queuing), WFQ(Weight Fair Queuing)아 같은 공평 큐잉 기법들에 대한 연구가 필요하다. 본 논문에서는 WFQ와 같은 공평 큐잉 기법을, 실시한 비디오 패킷 전송에 효과적으로 사용하기 위한 방법(AWF2Q+)을 제안하였다. FIFO, WFQ, AWF2Q+의 서비스 품질(PSNR)에 대한 비교, 분석을 통해 제안한 알고리즘이 실시간 비디오 서비스의 품질(PSNR)을 향상할 수 있다는 것을 보였다.

• Journal of KIISE:Information Networking
• /
• v.27 no.3
• /
• pp.315-322
• /
• 2000

네트워크에서 QoS를 보장하기 위해 최근에 제안되는 패킷 스케줄링 알고리즘은 대부분 우선 순위에 입각한 패킷 전송 서비스를 한다. 이러한 우선 순위를 유지하기 위한 큐의 관리에는 많은 비용이 들므로 QoS를 보장하는 네트워크에서 우선 순위 큐의 관리 비용을 줄이는 노력이 필요하다. 패킷 스케줄링 알고리즘 중 RPO+(Rotate Priority Queue)는 우선 순위 FIFO(First in first out)큐를 사용하여 주기 적으로 재명명되는 패킷 스케줄링 알고리즘이다. FIFO 큐에 패킷들을 근사 정렬하여 패킷의 우선 순위를 유지하므로 계산 복잡도를 줄이지만, 패킷 우선 순위를 유지하기 위해 2배(2P)의 큐를 필요로 한다.[1] 본 논문에서는 필요한 큐의 개수를 P개의 큐로 제한하여 큐에 대한 관리 비용을 줄였으며 엔터프라이즈 환경에서 애플리케이션이 요구하는 서비스 특성에 따라 클래스로 구분하여 적합한 패킷 스케줄링 서비스를 제공하는 알고리즘을 제시한다. 본 기법은 추가적인 오버플로우 큐를 관리하고 패킷 어드미션 컨트롤러를 통해 패킷 전송 지연 시간을 제한함으로 다양한 애플리케이션의 네트워크 QoS 요구를 보장하고 패킷 전손 효율을 높였다.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.15 no.3
• /
• pp.243-251
• /
• 1990

In this paper, the performances of bandwidth allocation strategies for wideband ISDN have been studied through the computer simulation. In general, the performance of multichannel bandwidth allocation method is superior to that of single channel bandwidth allocation method with respect to the throughtput, delay and blocking probability. Also, when the FIFO service scheme is used, it is shown that the throughput, delay characteristics and blocking probability for each traffic are almost similar. On the other hand, the priority service scheme being used, the performances of traffic with high priority are much better than that of traffic with low priority in the view of throughput, delay and blocking probability. Finally, for the FIFO and priority service disciplines, it can be seen that the multichannel bandwidth allocation method is more suitable than the single channel bandwidth allocation strategy in the case of serving various traffic.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.11
• /
• pp.1377-1383
• /
• 2019

Histogram equalization is the most frequently used algorithm for image enhancement. Its hardware implementation significantly outperforms in time its software version. The overall performance of FPGA-based implementation of histogram equalization can be improved by applying pipelining in the design and by exploiting the multipliers and a lot of SRAM blocks which are embedded in recent FPGAs. This work proposes how to implement a fast histogram equalization circuit for 8-bit gray level images. The proposed design contains a FIFO to perform equalization on an image while the histogram for next image is being calculated. Because of some overlap in time for histogram equalization, embedded multipliers and pipelined design, the proposed design can perform histogram equalization on a pixel nearly at a clock. And its dual parallel version outperforms in time almost two times over the original one.

• Journal of applied mathematics & informatics
• /
• v.18 no.1_2
• /
• pp.431-439
• /
• 2005

The aim of this paper is to derive the analytical solution of the queue: $M/E_{r}/1/k/N$ for machine interference system with balking and reneging considering the discipline FIFO. Some measures of effectiveness and some special cases are obtained.

• Communications of the Korean Mathematical Society
• /
• v.16 no.4
• /
• pp.659-666
• /
• 2001

The aim of this paper is to derive the analytical so-lution of the queue: H$_{r}$/M/c/k/N for machine interference with balking and reneging, and FIFO (first in, first out) service disci-pline.e.

• Proceedings of the KIEE Conference
• /
• 2004.11c
• /
• pp.237-239
• /
• 2004

Wireless LAN Voice over IP(VoIP) equipment needs Quality-of-Service(QoS) with priority for processing real-time traffic. This paper shows transmit function implementation of wireless LAN(WLANs) media access control(MAC) support VoIP, and it has an advantage of guarantee of QoS and is adaptable to VoIP or mobile wireless equipment. The IEEE 802.11e standard in progress has four queues according to four access categories(AC) for transmit and the MAC transmits the data based on EDCA. The value of AC is from AC0 to AC3 and AC3 has the highest priority. The transmit method implemented at this paper ensure QoS using one transmit FIFO in hardware since real-time traffic data and non real-time traffic data has the different priority. The device driver classifies real-time data and non real-time data and transmit data to hardware with information about data type. The hardware conducts shorter backoff and selects faster AIFS slot for real-time data than it for non real-time data. Therefor It make give the real-time traffic data faster channel access chance than non real-time data and enhances QoS.

• Journal of Advanced Navigation Technology
• /
• v.10 no.1
• /
• pp.70-78
• /
• 2006

This paper has addressed the scheme to design single rate Rate Adaptive Shaper (srRAS) proposed in RFC2963. srRAS is the shaper used in conjugation with downstream single rate Three Color Marker (srTCM) described in RFC269. it is tail-drop First Input First Out (FIFO) queue that is drained at a variable rate. srTCM meters IP packet streams from srRAS and marks its packets to be either green, yellow, or red. This shaper has been proposed to use at the ingress of differentiated services networks providing AF PHB. And then srRAS can reduce the burstiness of the upstream traffic of srTCM. This paper addresses algorithm, architecture of srRAS, and the scheme to implement srRAS using Field-Programmable Gate Arrays (FPGA) and the related technology.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.28 no.11B
• /
• pp.999-1006
• /
• 2003

In the paper, we investigate the impact of handoff on the packet delivery in the Mobile IPv6 networks, where the smooth handoff is adopted. That is measured by an 'unstable time period (UTP)', a 'silence time period(STP)', and a 'handoff time period (HTP)' in the mobile node's perspective. Then, we propose a queuing model to get the exact value of the handoff transient time. The numerical results show that the queuing delay for the handoff packets and the involved link (or route) capacities affect the estimated UTP, STP, and HTP. On the other hand, the damage of application caused by handoff will increases when the handoff transient time becomes longer. We show that the priority scheduling method can achieve shorter STP and UP than the FIFO scheduling method that is generally used in best-effort IP network.