• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.12
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• pp.61-68
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• 2004

Wireless mobile communication systems request high speed mobility and high speed data transmission capability. In order to meet the requirements, OFDM(Orthogonal Frequency Division Multiplex) is mainly adopted in the physical layer of the wireless systems. In commercial wireless mobile systems, IEEE802.(11a, 16e, etc) series seem to be used as the modulation method. For supporting multiple air-interfaces in a wireless mobile system, different kinds of OFDM based modulation methods should be supported in one modem chip. It requires a variable point IFFT/FFT or reconfigurable IFFT/FFT processor. In this paper, we propose the design method of a reconfigurable IFFT/FFT processor. In addition, it is shown that a reconfigurable IFFT/FFT processor can he implemented by using the proposed method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8B
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• pp.787-795
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• 2002

This paper presents the architecture and the implementation of a 2K/4K/8K-point complex Fast Fourier Transform(FFT) processor for Orthogonal Frequency-Division Multiplexing (OFDM) system. The architecture is based on the Cooley-Tukey algorithm for decomposing the long DFT into short length multi-dimensional DFTs. The transposition memory, shuffle memory, and memory mergence method are used for the efficient manipulation of data for multi-dimensional transforms. Booth algorithm and the COordinate Rotation DIgital Computer(CORDIC) processor are employed for the twiddle factor multiplications in each dimension. Also, for the CORDIC processor, a new twiddle factor generation method is proposed to obviate the ROM required for storing the twiddle factors. The overall 2K/4K/8K-FFT processor requires 600,000 gates, and it is implemented in 1.8 V, 0.18 ${\mu}m$ CMOS. The processor can perform 8K-point FFT in every 273 ${\mu}s$, 2K-point every 68.26 ${\mu}s$ at 30MHz, and the SNR is over 48dB, which are enough performances for the OFDM in DVB-T.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.15-23
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• 2009

This paper presents a novel high-speed, low-complexity flexible 128/64-point $radix-2^4$ FFT/IFFT processor for the applications in high-throughput MIMO-OFDM systems. The high radix multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. The proposed processor not only supports the operation of FFT/IFFT in 128-point and 64-point but can also provide a high data processing rate by using a four-parallel data-path scheme. Furthermore, the proposed design has a less hardware complexity compared with traditional 128/64-point FFT/IFFT processors. Our proposed processor has a high throughput rate of up to 560Msample/s at 140MHz while requiring much smaller hardware expenditure satisfying IEEE 802.11n standard requirements.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.3
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• pp.114-129
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• 1993

A FFT array processor algorithm and architecture which anc use a minumum required number of simple, duplicate multiplier-adder processing elements according to various computation speed, will be presented. It is based on the p fold symmetry in the radix p constant geometry FFT butterfly stage with shuffled inputs and normally ordered outputs. Also, a methodology to implement a high performance high radix FFT with VLSI by constructing a high radix processing element with the duplications of a simple lower radix processing element will be discussed. Various performances and the trade-off between computation speed and hardware complexity will be evaluated and compared. Bases on the presented architecture, a radix 2, 8 point FFT processing element chip has been designed and it structure and the results will be discusses.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.12
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• pp.87-94
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• 2003

In this paper, we propose an IFFT/FFT design method to minimize quantization error in IEEE 802.11a WLAN. In the proposed algorithm, the twiddle coefficient of IFFT/FFT processor is manipulated by the statistics distribution of the input data at each stage. We applies this algorithm to radix-2/$^2$ SDF architecture. Both IFFT and FFT processor shares the circuit blocks cause to the symmetric architecture. The maximum quantization error with the 10 bits length of the input and output data is 0.0021 in IFFT and FFT that has a self-loop structure with the proposed method. As a result, the proposed architecture saves 3bits for the data to keep the same resolution compared with the conventional method.

• Journal of IKEEE
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• v.24 no.3
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• pp.797-802
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• 2020

In this paper, we presents the design and implementation results of the FFT processor, which supports 4096 points of operation with less memory by sharing several memory used in the base-4 systolic array FFT processor into one memory. Sharing memory provides the advantage of reducing the area, and also simplifies the flow of data as I/O of the data progresses in one memory. The presented FFT processor was implemented and verified on the FPGA device. The implementation resulted in 51,855 CLB LUTs, 29,712 CLB registers, 8 block RAM tiles and 450 DSPs, and confirmed that the memory area could be reduced by 65% compared to the existing base-4 systolic array structure.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.2
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• pp.144-150
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• 1990

This paper describes radix-4 Fast Fourier Transform (FFT) Processor designed with the new twice perfect shuffle developed from a perfect shuffle used in radix-2 FFT algorithm. The FFT Processor consists of a butterfly arithmetic circuit, address generators for input, output and coefficient, input and output registers and controller. Also, it requires the external ROM for storage of coefficient and RAM for input and output. The butterfly circuit includes 12 bit-serial ($16{\times}8$) multipliers, adders, subtractors and delay shift registers. Operating on 25 MHz two phase clock, this processor can compute 256 point FFT in 6168 clocks, i.e. 247 us and provides flexibility by allowing the user to select any size among 4,16,64,and256points. Being fabricated with 2-um double metal CMOS process, it includes about 28000 transistors and 55 pads in $8.0{\times}8.2mm^2$area.

• Proceedings of the KIEE Conference
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• 2002.07b
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• pp.1071-1074
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• 2002

In this paper, power quality analysis system is proposed where voltage or current waveforms are nonsinusoidal. The proposed system relies on the FFT algorithm to compute real and reactive power. The advantage of system is that harmonic analysis is carried out on a period of the input signal. The proposed system is based on FFT processor which is designed using VHDL(Very high-speed integrated circuit Hardware Description Language). In the design of FFT processor, radix- $2^2$ is adopted to reduce several complex multipliers for twiddle factor. Complex multiplier is implemented as only shifters and adders. Therefore, the system is able to have both high hardware efficiency and high performance.

• The Journal of the Korea institute of electronic communication sciences
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• v.3 no.2
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• pp.86-92
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• 2008

Othogonal Frequency Division Multiplexing(OFDM) has been taken notice of 4th generation communication method because it has a merit of high data rate(HDR). To realize HDR communication, The OFDM a s high efficient Fast-Fourier-Transform (FFT)/Inversion FFT (IFFT) processor. Currently OFDM is realized by Digital Signal Processor(DSP) but it consumes a lot of Power. Therefore, current-mode FFT LSI has been proposed for compensation of this demerit. In this paper, we propose IVC for current-mode FFT LSI. From the simulation result, the output value of IVC is more than 3V when the value of FFT Block output is more than $7.35{\mu}A$. The output value of IVC is lower than 0.5V when the value of FFT Block output is lower than $0.97{\mu}A$. Designed IVC Low-power Current mode FFT LSI will contribute to the operation of current-mode FFT LSI and the development of next generation wireless communication systems.

• Journal of the Korean Institute of Intelligent Systems
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• v.12 no.2
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• pp.135-143
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• 2002

In this study, Multi-Values Logic processor was designed using the basic circuit of the electric current mode CMOS. First of all, binary FFT(Fast courier Transform) was extended and high-speed Multi-Valued Logic processor was constructed using a multi valued logic circuit. Compared with the existing two-valued FFT, the FFT operation can reduce the number of transistors significantly and show the simplicity of the circuit. Moreover, for the construction of amount was used inside the FFT circuit with the set of redundant numbers like {0, 1, 2, 3}. As a result, the defects in lines were reduced and it turned out to be effective in the aspect of normality an regularity when it was used designing VLSI(Very Large Scale Integration). To multiply FFT, the time and size of the operation was used toed as LUT(Lood Up Table).