• The Journal of Korean Institute of Communications and Information Sciences
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• 제34권12C호
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• pp.1167-1176
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• 2009

In This Paper, we introduce an efficient IFFT design technique named for transmitter of OFDM (Orthogonal Frequency Division Multiplexing) system. In OFDM system, a cyclic prefix is inserted in forepart of OFDM symbol to prevent ICI(Inter-channel Interference) and ISI (Inter-symbol Interference). Attaching cyclic prefix causes delay in storing and copying IFFT result. The proposed IFFT removes this delay because its output is cyclic shifted by the length of cyclic prefix. So we can make a complete OFDM symbol by just copying the forepart of IFFT output to the end. In many cases, the length of cyclic prefix is 1/2n of FFT size, and this IFFT does not require additional hardware complexity and it does not cause any performance degradation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권6호
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• pp.39-48
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• 2005

This paper proposes a reconfigurable coprocessor for communication systems, which can perform high speed computations and various functions. The proposed reconfigurable coprocessor can easily implement communication operations, such as scrambling, interleaving, convolutional encoding, Viterbi decoding, FFT, etc. The proposed architecture has been modeled by VHDL and synthesized using the SEC 0.18$\mu$m standard cell library. The gate count is about 35,000 gates and the critical path is 3.84ns. The proposed coprocessor can reduced about $33\%$ for FFT operations and complex MAC, $37\%$ for Viterbi operations, and $48\%\~84\%$ for scrambling and convolutional encoding for the IEEE 802.11a WLAN standard compared with existing DSPs. The proposed coprocessor shows Performance improvements compared with existing DSP chips for communication algorithms.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제12권4호
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• pp.1867-1875
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• 2011

In this paper, a low-area 256-point FFT structure is proposed. For low-area implementation CSD(Canonic Signed Digit) multiplier method is chosen. Because multiplication type should be less for efficient CSD multiplier application to the FFT structure, the Radix-$4^2$ algorithm is chosen for those purposes. After, in the proposed structure, the number of multiplication type is minimized in each multiplication block, the CSD multipliers are applied for implementation of multiplication. Furthermore, in CSD multiplier implementation, cell-area is more reduced through common sub-expression sharing(CSS). The Verilog-HDL coding result shows 29.9% cell area reduction in the complex multiplication part and 12.54% cell area reduction in overall 256-point FFT structure comparison with those of the conventional structure.

• Journal of Sensor Science and Technology
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• 제24권3호
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• pp.169-174
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• 2015

In this study, we developed a system to detect the various defects in the metallic objects using the phenomenon that the defects cause the changes of the natural resonant frequencies. Our system consists of a FFT Amp, an Auto Impact Hammer, a Hammer controller and a PC. Auto Impact Hammer creates vibrations in the metallic objects when tapped on the surface. These vibrational signals are converted to the voltage signals by an acceleration sensor attached to the metallic part surface. These analog voltage signals were fed into an ADC (analog-digital converter) and an FFT (fast fourier transform) conversion in the FFT Amp to obtain the digital data in the frequency domain. Labview graphical program was used to process the digital data from th FFT amp to display the spectrum. We compared those spectra with the standard spectrum to find the shifts in the resonant frequencies of the metal parts, and thus detecting the defects. We used PCB's acceleration sensor and TI's TMS320F28335 DSP (digital signal processor) to obtain the resolution of 2.93 Hz and to analyze the frequencies up to 44 kHz.

• Proceedings of the KIEE Conference
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1449-1453
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• 1987

A microprogrammable Bit Slice Sinal Processor for image processing is implemented. Processing speed is increased by the parallelism in horizontal microprogram using 120bits microcode, pipelined architecture, 2 bank memory switching that interfaces with the Host through DMA, a variable clock control, overflow checking H/W,look-up table method and cache memory. With this processor, a DCT algorithm which uses 2-D FFT is performed. The execution time for $512{\times}512{\times}8$ image is 12 sec when 16 bit operation is runned, and the recovered image has acceptable quality with MSE 0.276%.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2001년도 제14회 신호처리 합동 학술대회 논문집
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• pp.261-264
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• 2001

본 논문에서는 OFDM 시스템용 복조기의 구현에 가장 핵심적인 소자인 2K/4K/8K-point FFT 프로세서를 제안하였다. 구현된 프로세서는 30MHz 시스템 클럭에 서 8,192개의 복소 입력 샘플을 273㎲에 2,048개의 복소 입력 샘플을 68.26㎲에 수행함으로써 OFDM방송에서 요구하는 심볼 fp이트의 데이터를 처리할 수 있다. 기본 구조는 1차원 DFT를 작은 크기의 2차원 DFT로 변환할 수 있는 쿨리-투키 알고리듬을 적용하였으며 다차원 DFT 변환에 적합한 전치 메모리와 셔플 메모리를 사용하였다. 복소 곱셈기는 기존의 방법보다 더 효율적인 메모리 구조를 갖는 CORDIC 프로세서를 사용하였으며 제안하는 트위들팩터 발생 방법은 트위들팩터를 저장하기 위한 ROM의 크기를 효과적으로 줄일 수 있다.

• Proceedings of the IEEK Conference
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(3)
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• pp.161-164
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• 2000

We propose the genetic algorithm to apply three kinds of FFT data flows to be considered the overhead for the data exchange between processors that have the multi-scheduling problem on parallel computer In the design of genetic algorithm, we propose the chromosome representation which can simply encode and decode a solution without any heuristic information, the evaluation function to be considered an efficiency of processor, and the genetic operator to inherit a superior gene from their parents. And we saw that the simulation result can verify better performance than the existing algorithm(BEA : binary exchange algorithm)in the face of execution time.

• Journal of the Korea Institute of Military Science and Technology
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• 제9권1호
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• pp.109-116
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• 2006

This paper presents a real time distance measuring device using a W-band linear frequency modulated continuous wave(FMCW) radar and TMS320C6701 digital signal processor(DSP). We used FFT operation for measuring distance with the beat signals and the results of FFT could be converted to distance with ease. We presented how to implement a real time miniaturized hardware system including network protocols using a single DSP core. Also how to control the modulation signal of FMCW system to compensate the VCO nonlinearity using the Time Gating control of DSP is presented. We have shown that the proposed system has good performances for measuring distance in real time via outdoor environment experiments.

• Journal of the Korean Institute of Telematics and Electronics
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• 제23권6호
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• pp.944-949
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• 1986

By improving the ability of arithmatic processing with an arithmatic processor in a microcomputer and realizing the data input system for real time analysis, an FFT analyzer that is usable within the range of audio frequency is designed and constructed. The input signal passes through a gain programmable pre-amplifier and anti-aliasing lowpass filter into an analogditital converter to be converted into digital form. The converted input data is processed by an Apple II microcomputer. The results of the processing are displayed using a microcomputer display unit and can be copied on a printer or stored in a floppy disk.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제21권6호
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• pp.49-55
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• 2021

Recently, a small tracking radar requires the development of a small millimeter wave tracking radar having a high range resolution that can acquire and track a target in various environments and disable the target system with a single blow. Small millimeter wave tracking radar with high range resolution needs to implement a signal processor that can process wide bandwidth signals in real time and meet the requirements of small tracking radar. In this paper, we designed a signal processor that can perform the role and function of a signal processor for a small millimeter wave tracking radar. The signal processor for the small millimeter wave tracking radar requires the real-time processing of input signal of OOOMHz center frequency and OOOMHz bandwidth from 8 channels. In order to satisfy the requirements of the signal processor, the signal processor was designed by applying the high-performance FPGA (Field Programmable Gate Array) and ADC (Analog-to-digital converter) for pre-processing operations, such as DDC (Digital Down Converter) and FFT (Fast Fourier Transform). Finally, the signal processor of the small millimeter wave tracking radar was verified via performance test.