• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.3.1-3.1
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• 2011

Over the past decade, the major efforts for lowering the cost of electronics has been devoted to increasing the packaging efficiency of the integrated circuits (ICs), which is defined by the ratio of all devices on system-level board compared to the area of the board, and to working on a larger but cheaper substrates. Especially, in flexible electronics, the latter has been the favorable way along with using novel nanomaterials that have excellent mechanical flexibility and electrical properties as active channel materials and conductive films. Here, the tool for achieving large area patterning is by printing methods. Although diverse printing methods have been investigated to produce highly-aligned structures of the nanomaterials with desired patterns, many require laborious processes that need to be further optimized for practical applications, showing a clear limit to the design of the nanomaterial patterns in a large scale assembly. Here, we demonstrate the alignment of highly ordered and dense silicon (Si) NW arrays to anisotropically etched micro-engraved structures using a simple evaporation process. During evaporation, entropic attraction combined with the internal flow of the NW solution induced the alignment of NWs at the corners of pre-defined structures. The assembly characteristics of the NWs were highly dependent on the polarity of the NW solutions. After complete evaporation, the aligned NW arrays were subsequently transferred onto a flexible substrate with 95% selectivity using a direct gravure printing technique. As proof-of-concept, flexible back-gated NW field effect transistors (FETs) were fabricated. The fabricated FETs had an effective hole mobility of 0.17 $cm2/V{\cdot}s$ and an on/off ratio of ${\sim}1.4{\times}104$. These results demonstrate that our NW gravure printing technique is a simple and effective method that can be used to fabricate high-performance flexible electronics based on inorganic materials.

• Clinical and Experimental Reproductive Medicine
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• v.46 no.4
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• pp.178-188
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• 2019

Objective: To determine the clinical pregnancy (CP) and live birth (LB) rates arising from frozen embryo transfers (FETs) that had been generated under the influence of in vitro fertilization (IVF) adjuvants given to women categorized as poor-prognosis. Methods: A registered, single-center, retrospective study. A total of 1,119 patients with first FETs cycle include 310 patients with poor prognosis (109 treated with growth hormone [GH], (+)GH group vs. 201 treated with dehydroepiandrosterone, (-)GH group) and 809 patients with good prognosis (as control, (-)Adj (Good) group). Results: The poor-prognosis women were significantly older, with a lower ovarian reserve than the (-)Adj (Good) group, and demonstrated lower chances of CP (p< 0.005) and LB (p< 0.005). After adjusting for confounders, the chances of both CP and LB in the (+)GH group were not significantly different from those in the (-)Adj (Good) group, indicating that the poor-prognosis patients given GH had similar outcomes to those with a good prognosis. Furthermore, the likelihood of LB was significantly higher for poor-prognosis women given GH than for those who did not receive GH (p< 0.028). This was further confirmed in age-matched analyses. Conclusion: The embryos cryopreserved from fresh IVF cycles in which adjuvant GH had been administered to women classified as poor-prognosis showed a significant 2.7-fold higher LB rate in subsequent FET cycles than a matched poor-prognosis group. The women with a poor prognosis who were treated with GH had LB outcomes equivalent to those with a good prognosis. We therefore postulate that GH improves some aspect of oocyte quality that confers improved competency for implantation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.1
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• pp.11-15
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• 1976

In a MOSFET multivibrator, the gate do not hold into a constant clamp voltage during a conduction period. The analysis of the operation and the 43sign of a MOSFET multivibrator circuit are much more discult than that using a bipolar transistor and a electron tube because of above reason. And therefore, in the designing procedures of the MOSFET monostable multivibrator of this paper, a graphical method is adopted in order to analyze and design easily. The voltage gain curves of the both FETs are drawn using a parameter the voltage Vc across the coupling condenser, and the curves are utilized to investigate the voltages of the drains and the gates and determine the gate bias voltage. The diagram gives also important informations for the design of the multivibrator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.1
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• pp.83-88
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• 2002

To increase the device linearities and the breakdown-voltages of FETs, $Al_{0.25}$G $a_{0.75}$As/I $n_{0.25}$G $a_{0.75}$As/A $l_{0.25}$G $a_{0.75}$As partially doped channel FET(DCFET) structures are proposed. The metal insulator-semiconductor(MIS) like structures show the high gate-drain breakdown voltage(-20V) and high linearities. We propose a partially doped channel structure to enhance the device linearity to the homogeneously doped channel structure. The physics of partially doped channel structure is investigated with 2D device simulation. The devices showed the small ripple of the current cut-off frequency and the power cut-off frequency over the wide bias range. bias range.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.4 s.346
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• pp.23-30
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• 2006

This paper describes the short-channel effect(SCE), corner effect of nano-scale MuGFETs(Multiple-Gate FETs) by three-dimensional simulation. We can extract the equivalent gate number of MuGFETs(Double-gate=2, Tri-gate=3, Pi-gate=3.14, Omega-gate=3.4, GAA=4) by threshold voltage model. Using the extracted gate number(n) we can calculate the natural length for each gate devices. We established a scaling theory for MuGFETs, which gives a optimization to avoid short channel effects for the device structure(silicon thickness, gate oxide thickness). It is observed that the comer effects decrease with the reduction of doping concentration and gate oxide thickness when the radius of curvature is larger than 17 % of the channel width.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.434.2-434.2
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• 2014

We observe enhanced pH response of solution-gated field-effect transistors (SG-FET) having 1D-2D hybrid channel of vertical grown ZnO nanorods grown on CVD graphene (Gr). In recent years, SG-FET based on Gr has received a lot of attention for biochemical sensing applications, because Gr has outstanding properties such as high sensitivity, low detection limit, label-free electrical detection, and so on. However, low-defect CVD Gr has hardly pH responsive due to lack of hydroxyl group on Gr surface. On the other hand, ZnO, consists of stable wurtzite structure, has attracted much interest due to its unique properties and wide range of applications in optoelectronics, biosensors, medical sciences, etc. Especially, ZnO were easily grown as vertical nanorods by hydrothermal method and ZnO nanostructures have higher sensitivity to environments than planar structures due to plentiful hydroxyl group on their surface. We prepared for ZnO nanorods vertically grown on CVD Gr (ZnO nanorods/Gr hybrid channel) and to fabricate SG-FET subsequently. We have analyzed hybrid channel FETs showing transfer characteristics similar to that of pristine Gr FETs and charge neutrality point (CNP) shifts along proton concentration in solution, which can determine pH level of solution. Hybrid channel SG-FET sensors led to increase in pH sensitivity up to 500%, compared to pristine Gr SG-FET sensors. We confirmed plentiful hydroxyl groups on ZnO nanorod surface interact with protons in solution, which causes shifts of CNP. The morphology and electrical characteristics of hybrid channel SG-FET were characterized by FE-SEM and semiconductor parameter analyzer, respectively. Sensitivity and sensing mechanism of ZnO nanorods/Gr hybrid channel FET will be discussed in detail.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.482-483
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• 2011

Graphene is a good candidate for the future nano-electronic materials because it has excellent conductivity, mobility, transparency, flexibility and others. Until now, most graphene researches are focused on the nano electronic device applications, however, biological application of graphene has been relatively less reported. We have fabricated a deoxyribonucleic acid (DNA) conjugated graphene field-effect transistor (FET) and measured the electrical transport characteristics. We have used graphene sheets grown on Ni substrates by chemical vapour deposition. The Raman spectra of graphene sheets indicate high quality and only a few number of layers. The synthesized graphene is transferred on top of the substrate with pre-patterned electrodes by the floating-and-scooping method [1]. Then we applied adhesive tapes on the surface of the graphene to define graphene flakes of a few micron sizes near the electrodes. The current-voltage characteristic of the graphene layer before stripping shows linear zero gate bias conductance and no gate operation. After stripping, the zero gate bias conductance of the device is reduced and clear gate operation is observed. The change of FET characteristics before and after stripping is due to the formation of a micron size graphene flake. After combined with 30 base pairs single-stranded poly(dT) DNA molecules, the conductance and gate operation of the graphene flake FETs become slightly smaller than that of the pristine ones. It is considered that DNA is to be stably binding to the graphene layer due to the ${\pi}-{\pi}$ stacking interaction between nucleic bases and the surface of graphene. And this binding can modulate the electrical transport properties of graphene FETs. We also calculate the field-effect mobility of pristine and DNA conjugated graphene FET devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.134-142
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• 2010

A comparative study on the trade-off between the drive current and the total gate capacitance in double-gate (DG) and triple-gate (TG) FinFETs is performed by using 3-D device simulation. As the first result, we found that the optimum ratio of the hardmask oxide thickness ($T_{mask}$) to the sidewall oxide thickness ($T_{ox}$) is $T_{mask}/T_{ox}$=10/2 nm for the minimum logic delay ($\tau$) while $T_{mask}/T_{ox}$=5/1~2 nm for the maximum intrinsic gate capacitance coupling ratio (ICR) with the fixed channel length ($L_G$) and the fin width ($W_{fin}$) under the short channel effect criterion. It means that the TG FinFET is not under the optimal condition in terms of the circuit performance. Second, under optimized $T_{mask}/T_{ox}$, the propagation delay ($\tau$) decreases with the increasing fin height $H_{fin}$. It means that the FinFET-based logic circuit operation goes into the drive current-dominant regime rather than the input gate load capacitance-dominant regime as $H_{fin}$ increases. In the end, the sensitivity of $\Delta\tau/{\Delta}H_{fin}$ or ${{\Delta}I_{ON}}'/{\Delta}H_{fin}$ decreases as $L_G/W_{fin}$ is scaled-down. However, $W_{fin}$ should be carefully designed especially in circuits that are strongly influenced by the self-capacitance or a physical layout because the scaling of $W_{fin}$ is followed by the increase of the self-capacitance portion in the total load capacitance.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.11
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• pp.2228-2237
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• 1994

This paper describes the development of a Ku-band ($12.25GHz\sim12.75GHz$) SSPA intended as a replacement for TWTAs used in communication satelite transponder. The power stage of the amplifier consists of tow intrmally matched 8W FET divices combined using the branch-line coupler. To operate this stage, the drive stage has been designed with intermally matched 2W, 4W, 8W FET and two medium power FETs. The entire amplifier is made up by a aluminum chassis housing both the RF circuit and the bias circuitry. A regrlator/sequencing circuitry is used for FET biasing. The amplifier results implemented in this way show $41\pm0.3dB$ small-signal gain, 15W saturation power, a typical two tone $IM_3=-21.5dBc$ with single carrier backed off 5dB from saturation, $2^*/dBmax$ AM/PM conversion, and $3.47\pm0.25nsec$ group delay.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.28-31
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• 2004

This paper describe analysis active microstrip antenna with low noise amplifier at 900 MHz for mobile communication. The microstrip patch antenna is integrated with low noise amplifier on a permittivity 4.5 (Epoxy-FR4) and thickness of substrate 1.6 mm. Low noise amplifier is designed by using GaAs FETs. The analysis characteristics of antenna include return loss, input impedance, vswr, radiation pattarn, bandwidth and gain of antenna. Mesurement gain of antenna is shown 19.2435 dBi.