• ETRI Journal
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• 제38권1호
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• Bulletin of the Korean Chemical Society
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• 제28권11호
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• pp.2056-2060
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• 2007

A successful combination of “oxygen-assisted chemical vapor deposition (CVD) process” and Co catalyst nanoparticles to grow highly pure single walled carbon nanotubes (SWNTs) was demonstrated. Recently, it was reported that addition of small amounts of oxygen during CVD process dramatically increased the purity and yield of carbon nanotubes. However, this strategy could not be applied for discrete Fe nanoparticle catalysts from which appropriate yields of SWNTs could be grown directly on solid substrates, and fabricated into field effect transistors (FETs) quite efficiently. The main reason for this failure is due to the carbothermal reduction which results in SiO2 nanotrench formation. We found that the oxygen-assisted CVD process could be successfully applied for the growth of highly pure SWNTs by switching the catalyst from Fe to Co nanoparticles. The topological morphologies and p-type transistor electrical transport properties of the grown SWNTs were examined by using atomic force microscope (AFM), Raman, and from FET devices fabricated by photolithography.

• Journal of Power Electronics
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• 제16권1호
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• pp.84-92
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• 2016

Compared with Si MOSFETs, the GaN FET has many advantages in a wide band gap, high saturation drift velocity, high critical breakdown field, etc. This paper compares the electrical properties of GaN FETs and Si MOSFETs. The soft-switching condition and power loss analysis in a flyback-forward high gain DC/DC converter with a GaN FET is presented in detail. In addition, a comparison between GaN diodes and Si diodes is made. Finally, a 200W GaN FET based flyback-forward high gain DC/DC converter is established, and experimental results verify that the GaN FET is superior to the Si MOSFET in terms of switching characteristics and efficiency. They also show that the GaN diode is better than the Si diode when it comes to reverse recovery characteristics.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 춘계학술대회 논문집 센서 박막재료 반도체 세라믹
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• pp.186-189
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• 2003

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $ZrO_2$ and $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the $ZrO_2$ and $CeO_2$ layer. AES show no interdiffusion and the formation of amorphous $SiO_2$ layer is suppressed by using the $ZrO_2$ and $CeO_2$ film as buffer layer between the BLT film and Si substrate. The width of the memory window in the C-V curves for the $BLT/ZrO_2/Si$ and $BLT/CeO_2/Si$ structure is 2.94 V and 1.3V, respectively. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 추계학술대회 논문집 전기물성,응용부문
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• pp.183-186
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• 2004

The metal-ferroelectric-insulator-semiconductor(MFIS) capacitors were fabricated using a metalorganic decomposition (MOD)method. The $CeO_2$ thin films were deposited as a buffer layer on Si substrate and $Bi_{3.25}La_{0.75}Ti_3O_{12}$ (BLT) thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated by varying the $CeO_2$ layer thickness. The width of the memory window in the capacitance-voltage (C-V)curves for the MFIS structure decreased with increasing thickness of the $CeO_2$ layer. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) show no interdiffusion by using the $CeO_2$ film as buffer layer between the BLT film and Si substrate. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory field-effect-transistors (FETs) with large memory window.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.25-28
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• 1999

Metal ferroelectric semiconductor Field Effect- Transistors(MFSFET) with various gate electrodes, that are aluminum, platinum and poly -Si, using LiNbO$_3$/Si(100) structures were fabricated and the properties of the FETs have been discussed. The drain current of the state of FET with Pt electrode was more than 3 orders of magnitude larger than the state current at the same gate voltage of 1.5 V, 7.rich means the memory operation of the MFSFET. A write voltage as low as about $\pm$4 V, which is applicable to low power integrated circuits, was used for polarization reversal. The retention properties of the FET using Al electrode were quite good up to about 10$^3$s and using Pt electrode remained almost the same value of its initial value over 2 days at room temperature.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.23-26
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• 2003

The BLT thin film and MgO buffer layer were fabricated using a metalorganic decomposition method and the DC sputtering technique. The MgO thin film was deposited as a buffer layer on $SiO_2/Si$ and BLT thin films were used as a ferroelectric layer. The electrical of the MFIS structure were investigated by varying the MgO layer thickness. TEM showsno interdiffusion and reaction that suppressed by using the MgO film as abuffer layer. The width of the memory window in the C-Y curves for the MFIS structure decreased with increasing thickness of the MgO layer Leakage current density decreased by about three orders of magnitude after using MgO buffer layer. The results show that the BLT and MgO-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2009년도 제38회 동계학술대회 초록집
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• pp.63-63
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• 2010

Ability to transport extracted carriers from NQDs is essential for the development of most NQD based applications. Strategies to facilitate carrier transport while preserving NQDs' optical characteristics include: 1) Fabricating neat films of NQDs with modified surfaces either by adapting series of ligands with certain limitations or by applying physical processes such as heat annealing 2) Coupling of NQDs to one-dimensional nanostructures such as single walled carbon nanotubes (SWNTs) or various types of nanowires. NQD-nanowire hybrid nanostructures are expected to facilitate selective wavelength absorption, charge transfer to 1-D nanostructures, and efficient carrier transport. Even with the vast interests in using NQD-SWNT hybrid materials in optoelectric applications, still, no reports so far have clearly elucidated the optoelectric behavior when they were assembled on the FET mainly because the complexity involving in both components in their preparation and characterization. We have monitored the optical properties of both components (NQDs, SWNTs) from the synthesis, to the assembly, and to the device. More importantly, by using pyridine molecules as a linker to non-covalently attach NQDs to SWNTs, we were able to assemble NQDs on SWNTs with precise density control without harming their electronic structures. Furthermore, by measuring electrical signals from the fabricated aligned SWNTs-FET using dielectrophoresis (DEP), we were able to elucidate the charge transfer mechanism.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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• pp.271.2-271.2
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• 2013

열화학 기상 증착법은 반도체 산업에서 대면적으로 소자를 양산할 수 있는 방법 중의 하나로서, 그래핀, 이황화 몰리브덴과 같은 이차원 물질의 합성법으로 널리 이용되고 있다. 이런 이차원 물질은 층수에 따라 그 물성이 변화하므로, 층수 조절이 가능한 합성법의 필요성이 대두되고 있다. 열화학 기상 증착법으로 이차원 물질을 합성할 경우, 주요 변수로 성장 온도와 촉매 금속이 있으며 이를 적절히 조절함으로서 합성되는 그래핀의 결정성과 층수의 조절이 가능하다[1-3]. 또한, 이차원 반도체 물질로 전계효과 트랜지스터를 제작하는 경우, 얇은 두께로 인하여 표면의 환경에 민감하게 되므로 게이트 절연체가 중요한 문제로 대두되고 있으며, 이런 현상을 해결하고자 질화붕소(BN)과 같은 이차원 절연물질에 관심이 집중되고 있다. 본 연구에서는 이차원 절연체인 질화붕소의 표면 위에 그래핀을 합성하고자 하였다. 반데발스 성장법(van der Waals epitaxy growth method)으로 1. "BN/ SiO2" 2. "BN/ Ni" 3. "BN/ Cu"의 세 가지 기판을 이용하여 그래핀을 합성하였다. 합성된 그래핀의 결정성 및 층수를 확인하기 위해 라만 스펙트럼과 투과전사 현미경을 통하여 분석하였다. 또한, 이 방법으로 "그래핀/ 질화붕소/ 그래핀"과 같은 구조의 소자를 제작하여 전계효과 트랜지스터 특성을 살펴보았다.

• Journal of Power Electronics
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• 제18권6호
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• pp.1912-1919
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• 2018

The output capacitance of power semiconductor devices is important in determining the switching losses and in the operation of some resonant converter topologies. Thus, it is important to be able to accurately determine the output capacitance of a particular device operating at elevated power levels so that the contribution of the output capacitance discharge to switch-on losses can be determined under these conditions. Power semiconductor switch manufacturers usually measure device output capacitance using small-signal methods that may be insufficient for power switching applications. This paper shows how first principle methods are applied in a novel way to obtain more relevant large signal output capacitances of Gallium-Nitride (GaN) FETs using the drain-source voltage transient during device switch-off numerically. A non-linear capacitance for an increase in voltage is determined with good correlation. Simulations are verified using experimental results from two different devices. It is shown that the large signal output capacitance as a function of the drain-source voltage is higher than the small signal values published in the data sheets for each of the devices. It can also be seen that the loss contribution of the output capacitance discharging in the channel during switch-on correlates well with other methods proposed in the literature, which confirms that the proposed method has merit.