• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.564-564
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• 2012

Graphene has been emerged as a fascinating material for future nanoelectronic applications due to its extraordinally electronic properties. However, their zero-bandgap semimetallic nature is a major problem for applications in high performance field-effect transistors (FETs). Graphene nanoribbons (GNRs) with narrow widths (${\geq}10nm$) exhibit semiconducting behavior, which can be used to overcome this problem. In previous reports, GNRs were produced by several approaches, such as electron beam lithography patterning, chemically derived GNRs, longitudinal unzipping of carbon nanotubes, and inorganic nanowire template. Using these methods, however, the width distribution of GNRs was a quiet broad and substantial defects were inevitably occurred. Here, we report a novel approach for fabricating width-tailored GNRs by focused ion beam-assisted chemical vapor deposition (FIB-CVD). Width-tailored phenanthrene ($C_{14}H_{10}$) templates for direct growth of GNRs were prepared on $SiO_2$/Si substrate by FIB-CVD. The GNRs on the templates were synthesized at $900-1,050^{\circ}C$ with introducing $CH_4$ $(20sccm)/H_2$ (10 sccm) mixture gas for 10-300 min. Structural characterizations of the GNRs were carried out using Raman spectroscopy, scanning electron microscopy, and atomic force microscopy.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.16 no.2
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• pp.18-25
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• 2002

In this paper, We have researched about the Electronic Ballast for 250W HPS(High Pressure Sodium) lamp. This Electronic Ballast is capable to operate the Ignition and Steady State Using the Class D LCC resonant tank, and minimizing the full-bridge inverter's Switching Stress by implementation Quasi-square ZC-ZVS Soft Switching Method. And also, We have reduced the heat of MOS-FETs and high frequency switching surge noise using the RCD damp snubber. Therefore, We are sure that the developed ballast has the properties of the stable & reliable Control and the function of minimizing the total noise of the system.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.5
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• pp.663-671
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• 1999

The linearity of the GaAs FET power amplifier(PA) is greatly influenced by source and load impedance for the FETs. The third order intermodulation products, IM3, from the GaAs FET PA are investigated in relation with source and load impedance. From heuristic as well as analytic point of view, e.g., Volterra series analysis, is employed to analyze the effects of nonlinear circuit elements, gate-source capacitance, $C_{gs}$, and drain-source current, $I_{ds}$. The sweet spots where soure and load impedance produce the least intermodulation products are calculated and compared with the load and source pull data with good agreements. It also shows that source impedance has a greater effect on the intermodulation products than the load impedcnce.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.6
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• pp.514-520
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• 2002

In this paper, the study of a design and fabrication of the receiver MMIC mixer for L-band application is described. The mixer is composed of active LO and RF balun to integrate on a chip and applied a newly proposed bias circuit to compensate the process variations of active devices. The conversion gain of the mixer is -14 dB, IIP3 is approximately 4 dBm and port-to-port isolation is over 25 dB. The newly proposed bias circuit is composed of a few FETs and resistors, and can compensate the variation of the threshold voltage by the process variations, temperature changes and etc. The designed chip size is $1.4\;mm{\times}1.4\;mm$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.186-189
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• 2002

The MFIS capacitors were fabricated using a metalorganic decomposition method. Thin layers of $CeO_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X-ray diffraction was used to determine the phase of the BLT thin films and the quality of the $CeO_2$ layer. The morphology of films and the interface structures of the BLT and the $CeO_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 4.78 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.433-433
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• 2013

Graphene, $sp^2$-hybridized 2-Dimension carbon material, has drawn enormous attention due to its desirable performance of excellent properties. Graphene can be applied for many electronic devices such as field-effect transistors (FETs), touch screen, solar cells. Furthermore, indium tin oxide (ITO) is commercially used and sets the standard for transparent electrode. However, ITO has certain limitations, such as increasing cost due to indium scarcity, instability in acid and basic environments, high surface roughness and brittle. Due to those reasons, graphene will be a perfect substitute as a transparent electrode. We report the graphene synthesized by inductive coupled plasma enhanced chemical vapor deposition (ICP-PECVD) process on Cu substrate. The growth was carried out using low temperature at $400^{\circ}C$ rather than typical chemical vapor deposition (CVD) process at $1,000^{\circ}C$ The low-temperature process has advantage of low cost and also low melting point materials will be available to synthesize graphene as substrate, but the drawback is low quality. To improve the quality, the factor affect the quality of graphene was be investigated by changing the plasma power, the flow rate of precursors, the scenario of precursors. Then, graphene film's quality was investigated with Raman spectroscopy and sheet resistance and optical emission spectroscopy.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.2
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• pp.65-70
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• 2004

This paper presents a novel linearization scheme for a nonlinear RF amplifier It is based on the amplitude modulation with envelope signal. The 3rd order distortion generator is composed of two FETs and it adopts a balanced structure for the purpose of main carrier cancellation. The amplitude and phase of the IM3 component can be controlled at RF band. This predistorter is implemented and tested at the KOREA PCS Tx. band (1840∼1870MHz). Experimental results of two-tone test show that the IM3 cancellation is achieved about 30-40 ㏈ for the wide dynamic range. The adjacent channel power ratio is improved by over 10 ㏈ at the broad-band CDMA signal with a peak to average power ratio of l0㏈, and this improvement is maintained through a wide range of output power levels.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.11
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• pp.1170-1175
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• 2003

In this paper, the output power improvement of Push-Push FET DRO by adding the identical DR at the drain port as one used in the gate port, has been theoretically investigated. The investigation shows that the DR located between two microstrip lines locks the phase difference of two FET's outputs at 180 degree and improves the output power of Push-Push FET DRO. Since this effect can be used for correcting the impedance difference between two FETs output circuits and the electrical length error of the power combiner at the output circuit of Push-Push DRO, which may occur when fabricate the oscillator, the oscillator with an additional DR can be useful structure for fabricating oscillator.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.57 no.2
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• pp.135-139
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• 2008

MFISFETs with platinum electrode on the $LiNbO_3$/aluminum nitride/Si(100) structures were successfully fabricated and the properties of the FETs have been discussed. $I_D-V_G$ characteristics of MFISFETs for linear region (that is, 0.1 V of the drain voltage) showed hysteresis loop with a counter-clockwise trace due to the ferroelectric nature of $LiNbO_3$ films. A memory window (i.e., threshold voltage shift) of the fabricated device was about 2[V] for a sweep from -4 to +4[V]. The estimated field-effect electron mobility and transconductance on a linear region were 530[$cm^2/V{\cdot}s$] and 0.16[mS/mm], respectively. The drain current of 27[${\mu}A$] on the "on" state was more than 3 orders of magnitude larger than that of 30[nA] on the "off" state at the same "read" gate voltage of l.5[V], which means the memory operation of the MFISFET.

• Transactions on Electrical and Electronic Materials
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• v.16 no.3
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• pp.156-161
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• 2015

In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φ_m. As a consequence, the behavior of the leakage current improves with increased Φ_m. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.