• JSTS:Journal of Semiconductor Technology and Science
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• 제8권4호
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• pp.283-288
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• 2008

A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.873-879
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• 2016

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is $490{\mu}A$ from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.

• 한국전기전자재료학회논문지
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• 제16권10호
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• pp.865-870
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• 2003

The MFIS (Metal-Ferroelectric-Insulator-Semiconductor) capacitors were fabricated using a metalorganic decomposition method. Thin layers of CeO$_2$ were deposited as a buffer layer on Si substrate and BLT thin films were used as a ferroelectric layer. The electrical and structural properties of the MFIS structure were investigated. X -ray diffraction was used to determine the phase of the BLT thin films and the quality of the CeO$_2$ layer. The morphology of films and the interface structures of the BLT and the CeO$_2$ layers were investigated by scanning electron microscopy. The width of the memory window in the C-V curves for the MFIS structure is 2.82 V. The experimental results show that the BLT-based MFIS structure is suitable for non-volatile memory FETs with large memory window.

• 전기학회논문지
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• 제66권4호
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• pp.636-642
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• 2017

Recently, new power devices, SiC and GaN FETs, are commercialized. They are expected to change power electronics environments. They will raise operating frequencies of power electronic equipments. Accordingly, design method will be changed greatly. In this paper, an 1 MHz resonant converter with fully compensated coreless isolation transformer is proposed, where the primary voltage is proportional to the secondary current and the primary current to the secondary voltage. 30 W prototype is constructed and tested, and its usefulness is verified.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.770-772
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• 2002

A new dry-processing method of organic gate dielectric film in field-effect transistors (FETs) was proposed. The method use vapor deposition polymerization (VDP) that is continuous and low temperature process. It has the advantages of shadow mask patterning and dry processing in flexible low-cost large area applications. Here, 80 nm-thick Al as a gate electrode was evaporated through shadow mask. Gate insulators used two different polyimides. The one material was 4,4'-oxydiphtahlic anhydride (ODPA) and 4,4'-oxydianiline (ODA). Another was 2,2-bis(3,4-dicarboxyphenyl) Hexafluoropropane Dianhydride (6FDA) and 4,4' -oxydianiline (ODA). These were co-deposited by high-vaccum thermal-evapora and cured at 150 $^{\circ}C$ for 1 hour, respectively. Pentacene as a semiconductor and 100 nm-thick Au as a source and drain electrode were evaporated through shadow mask.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.290-293
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• 2002

For small capacity rectifier circuits such as these for consumer electronics and appliances, capacitor input type rectifier circuits are generally used. Consequently, various harmonics generated within the power system become a serious problem. Various studies of this effect have been presented previously. However, most of these employ switching devices, such as FETs and the like. The absence of switching devices makes systems more tolerant to over-load, and brings low radio noise benefits. We propose a power factor connection scheme using a LC resonant in commercial frequency without switching devices. In this method, It makes a sinusoidal wave by widening conduction period using the current resonance in commercial frequency, Hence, the harmonic characteristics can be significantly improved, where the lower order harmonics, such as the fifth and seventh orders are much reduced. The result are confirmed by the theoretical and experimental implementations.

• 센서학회지
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• 제16권4호
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• pp.313-318
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• 2007

Single-wall carbon nanotube field-effect transistors (SWCNT FETs) of top gate structure were fabricated in a conventional metal-oxide-semiconductor field effect transistor (MOSFET) with gate electrodes above the conduction channel separated from the channel by a thin $SiO_{2}$ layer. The carbon nanotubes (CNTs) directly grown using thin Fe film as catalyst by thermal chemical vapor deposition (CVD). These top gate devices exhibit good electrical characteristics, including steep subthreshold slope and high conductance at low gate voltages. Our experiments show that CNTFETs may be competitive with Si MOSFET for future nanoelectronic applications.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.158-158
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• 2011

A wide range of techniques for the direct-printing of functional materials have been developed for the fabrication of micro- and nanoscale structures and devices. Here we report a new direct patterning method, liquid bridge-mediated nanotransfer molding (LB-nTM), for the formation of two- or three-dimensional structures with feature sized as small as tens of nanometers over large areas up to 4". LB-nTM is based on the direct transfer of various materials from a mold to a substrate via a liquid bridge between them. The LB-nTM method was applied to the preparation of organic nanowire FETs on flexible substrates.

• EDISON SW 활용 경진대회 논문집
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• 제4회(2015년)
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• pp.357-364
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• 2015

In this work, we investigate the quantum effects exhibited from ultra-thin GAA(gate-all-around) Nanowire FETs for Sub 14nm Technology. We face designing challenges particularly short channel effects (SCE). However traditional MOSFET SCE models become invalid due to unexpected quantum effects. In this paper, we investigated various performance factors of the GAA Nanowire FET structure, which is promising future device. We observe a variety of quantum effects that are not seen when large scale. Such are source drain tunneling due to short channel lengths, drastic threshold voltage increase caused by quantum confinement for small channel area, leakage current through thin gate oxide by tunneling, induced source barrier lowering by fringing field from drain enhanced by high k dielectric, and lastly the I-V characteristic dependence on channel materials and transport orientations owing to quantum confinement and valley splitting. Understanding these quantum phenomena will guide to reducing SCEs for future sub 14nm devices.

• 한국전자파학회논문지
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• 제11권4호
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• pp.575-581
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• 2000

본 논문에서는 Vector Sum 방법을 이용한 새로운 구조의 능동 위상천이기를 제안하였고 그 위상천이기를 제 어할 독특한 디지털 방식의 위상 제어 방법을 제시하였다. 제안한 새로운 구조의 능동 위상천이기는 Wilkinson power combiner/divider, branch line 3 dB quadrature hybrid coupler, 그리고 dual gate FET(DGFET)를 사용 한 가변 이득 증폭기(VGA)를 이용하여 설계.제작하였다. 그리고 제작된 능동 위상천이기를 디지털 방식으로 동작시킴으로써 제안된 구조가 효율적으로 잘 동작하고 또한 제시된 디지혈 방식으로 제어하는 방법이 타당함을 보였다.