• Proceedings of the KIEE Conference
• /
• 1998.11c
• /
• pp.723-725
• /
• 1998

STI CMP process are substituting gradually for LOCOS(Local Oxidation of Silicon) process to be available below sub-0.5um technology and to get planarized. The other hand, STI CMP process(especially STI CMP with RIE etch back process) has some kinds of defect like Nitride residue, Torn Oxide defect, etc. In this paper, we studied how to reduce Torn Oxide defects after STI CMP with RIE etch back process. Although Torn Oxide defects which occur on Oxide on Trench area is not deep and not sever, Torn oxide defects on Moat area is sometimes very deep and makes the yield loss. We did test on pattern wafers witch go through Trench process, APCVD process, and RIE etch back process by using an REC 472 polisher, IC1000/SUV A4 PAD and KOH base slurry to reduce the number of torn defects and to study what is the root causes of torn oxide defects.

• Journal of the Korean Ceramic Society
• /
• v.27 no.4
• /
• pp.447-456
• /
• 1990

ZnWO4 single crystals were grown by Czochralski method. And the orientation of grown crystals were determined by Laue back reflection, and the crystals were siliced at (100), (010), (001) face before polishing. The morphologys and distribution of etch pits on each face were observed by optical microscopy. In the present study, we understood that dislocation distributjioon rely on shape of solid-liquid interface, and secondary phase acts on the dislocation source. We also observed dislocation trace(etch pits) of (100) slip plane on (010) cleavage plane.

• Journal of Sensor Science and Technology
• /
• v.13 no.4
• /
• pp.264-269
• /
• 2004

This paper describes on an advanced technology of 3C-SiC/Si(100) wafer direct bonding using PECVD oxide to intermediate layer for SiCOI(SiC-on-Insulator) structure because it has an attractive characteristics such as a lower thermal stress, deposition temperature, more quick deposition rate and higher bonding strength than common used poly-Si and thermal oxide. The PECVD oxide was characterized by ATR-FTIR. The bonding strength with variation of HF pre treatment condition was measured by tensile strength measurement system. After etch-back using TMAH solution, roughness of 3CSiC surface crystallinity and bonded interface was measured and analyzed by AFM, XRD, and SEM respectively.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.32A no.1
• /
• pp.200-205
• /
• 1995

The 1st and 2nd-order grating structure for long wavelength DFB(Distributed FeedBack) laser diodes are successfully fabricated on InP substrates by using electron beam lithography and reactive ion etch techniques, and also characterized non-destructively by diffraction analysis without removal of photo-resis layer. A new composite layer made by lifted-off Cr layer on thin SiO2 film is developed and used as an etch mask, because PMMA, the e-beamresist, is unsuitable for reactive ion etch of InP. In addition, it is experimentally confiremed that diffraction analysis makes it possible to predict the grating parameters, and the analysis can be used as a non-destructive on-line test to prevent incomplete gratings from being successively processed.

• Journal of the Korean Vacuum Society
• /
• v.8 no.4A
• /
• pp.490-495
• /
• 1999

In 0.18 $\mu \textrm m$ LOGIC device, the etch rate of NMOS polysilicons is different from that of PMOS polysilicons due to the state of polysilicon to manufacture gate line. To control the etch profile, we tested the ratio of $Cl_2$/HBr gas and the total chamber pressure, and also we reduced Back He pressure to get the vertical profile. In the case of manufacturing the gate photoresist line, we used Bottom Anti-Reflective Coating (BARC) to protect refrection of light. As a result we found that $CF_4O_2$ gas is good to etch BARC, because of high selectivity and good photoresist line profile after etching BARC. in the results of the characterization of plasma damage to the antenna effect of gate oxide, NO type thin film(growing gate oxide in 0, ambient followed by an NO anneal) is better than wet type thin film(growing gate oxide in $0_2+H_2$ ambient).

• International Journal of Control, Automation, and Systems
• /
• v.2 no.2
• /
• pp.256-262
• /
• 2004

Conventionally, profile non-uniformity has been characterized by relying on approximated profile with angle or anisotropy. In this study, a new non-uniformity model for etch profile is presented by applying a discrete wavelet to the image obtained from a scanning electron microscopy (SEM). Prediction models for wavelet-transformed data are then constructed using a back-propagation neural network. The proposed method was applied to the data collected from the etching of tungsten material. Additionally, 7 experiments were conducted to obtain test data. Model performance was evaluated in terms of the average prediction accuracy (APA) and the best prediction accuracy (BPA). To take into account randomness in initial weights, two hundred models were generated for a given set of training factors. Behaviors of the APA and BPA were investigated as a function of training factors, including training tolerance, hidden neuron, initial weight distribution, and two slopes for bipolar sig-moid and linear function. For all variations in training factors, the APA was not consistent with the BPA. The prediction accuracy was optimized using three approaches, the best model based approach, the average model based approach and the combined model based approach. Despite the largest APA of the first approach, its BPA was smallest compared to the other two approaches.

• 한국신재생에너지학회:학술대회논문집
• /
• 2009.11a
• /
• pp.347-347
• /
• 2009

결정질 태양전지의 공정에 있어서 호모지니어스(homogeneous)한 구조보다 향상된 변환효율을 얻기 위해 선택적 도핑 방법에 관한 연구가 활발하다. 선택적 도핑 방법이란 에미터(emitter) 층을 $n^{++}$ 영역과 $n^+$ 영역으로 나누어 향상된 전류밀도와 개방전압을 얻기 위한 방법이다. 본 연구에서 제시된 RIE 에치-백 구조는 다수의 선택적 도핑 방법 중 하나이다. 기존의 에치-백 구조는 전면 전극 형성 후 RIE 공정을 수행하기 때문에 전면 전극이 손상되고 RIE 데미지(damage)가 발생되는 문제점이 있었다. 그러나 본 연구에서 제시된 구조는 기존의 에치-백 구조와 달리 RIE 에칭 후 발생된 데미지를 제거하는 추가적인 공정인 질산 패시베이션(nitric acid passivation)이 수행되었다. 또한 본 연구에서 새롭게 제시된 블라킹 마스크 페이스트(blocking mask paste)는 기존의 에치-백 구조에서 발생된 전극 손상 문제를 해결해 주고 있다. 이러한 결과로 호모지니어스 구조보다 향상된 전류밀도 (35.77 mA/$cm^2$), 개방전압 (625 mV), FF (78.01%), 변환효율 (17.43%)를 얻었다.

• Journal of the Microelectronics and Packaging Society
• /
• v.28 no.4
• /
• pp.57-61
• /
• 2021

A formation process of indium bump arrays on micro-pillar structures is proposed. The space to form indium bump on the narrow structures can be secured applying the benzocyclobutene (BCB) planarization and its etch-back process. We exhibit a detailed overview of the process steps involved in the fabrication of 320×256 hybrid camera sensor for short-wavelength infrared (SWIR) detection. The shear strength of the BCB, which has undergone the different processes, is extracted by quartz crystal microbalance measurement. The shear strength of the BCB is three orders of magnitude higher than that of the indium bump itself. The measured dark current distribution of the fabricated SWIR camera sensor indicates the suggested process of indium bumps can be useful for embodying highly sensitive infared camera sensors.

• Journal of the Korean Vacuum Society
• /
• v.6 no.2
• /
• pp.103-108
• /
• 1997

Silicon field emitter arrays (FEAs) have been fabricated by a novel method employing a two-step tip etch and a spin-on-glass (SOG) etch-back process using double layered thermal/tetraethylortho-silicate (TEOS) oxides as a gate dielectric. A partial etching was performed by coating a low viscous photo resist and $O_2$ plasma ashing on order to form the double layered gate dielectric. A small gate aperture with low gate leakage current was obtained by the novel process. The hight and the end radius of the fabricated emitter was about 1.1 $\mu\textrm{m}$ and less than 100$\AA$, respectively. The anode emission current from a 256 tips array was turned-on at a gate voltage of 40 V. Also, the gate current was less than 0.1% of the anode current.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.523-523
• /
• 2012

As the wafer geometric requirements continuously complicated and minutes in tens of nanometers, the expectation of real-time add-on sensors for in-situ plasma process monitoring is rapidly increasing. Various industry applications, utilizing plasma impedance monitor (PIM) and optical emission spectroscopy (OES), on etch end point detection, etch chemistry investigation, health monitoring, fault detection and classification, and advanced process control are good examples. However, process monitoring in semiconductor manufacturing industry requires non-invasiveness. The hypothesis behind the optical monitoring of plasma induced ion current is for the monitoring of plasma induced charging damage in non-invasive optical way. In plasma dielectric via etching, the bombardment of reactive ions on exposed conductor patterns may induce electrical current. Induced electrical charge can further flow down to device level, and accumulated charges in the consecutive plasma processes during back-end metallization can create plasma induced charging damage to shift the threshold voltage of device. As a preliminary research for the hypothesis, we performed two phases experiment to measure the plasma induced current in etch environmental condition. We fabricated electrical test circuits to convert induced current to flickering frequency of LED output, and the flickering frequency was measured by high speed optical plasma monitoring system (OPMS) in 10 kHz. Current-frequency calibration was done in offline by applying stepwise current increase while LED flickering was measured. Once the performance of the test circuits was evaluated, a metal pad for collecting ion bombardment during plasma etch condition was placed inside etch chamber, and the LED output frequency was measured in real-time. It was successful to acquire high speed optical emission data acquisition in 10 kHz. Offline measurement with the test circuitry was satisfactory, and we are continuously investigating the potential of real-time in-situ plasma induce current measurement via OPMS.