• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.106-109
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• 2002

In the integrated systems, that is integrated digital TV(DTV) internet and home automation, like home server, is needed integration of digital TV video signal and computer graphic signal. The graphic signal is operating at the high speed and has time-divide-stream. So the re-request of data is not easy at the time of error detection. therefore EDAC algorithm is efficient. This paper presents the efficiency error detection auto correction(EDAC) for conversion of graphics signal to DTV video signal. A presented EDAC algorithms use the modified Hamming code for enhancing video quality and reliability. A EDAC algorithm of this paper can detect single error, double error, triple error and more error for preventing from incorrect correction. And it is not necessary an additional memory. In this paper The comparison between digital TV video signal and graphic signal, a EBAC algorithm and a design of conversion graphic signal to DTV signal with EDAC function is described.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.2126-2130
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• 2003

In the integrated systems, that is integrated digital TV(DTV) internet and home automation, like home server, is needed integration of digital TV video signal and computer graphic signal. The graphic signal is operating at the high speed and has time-divide-stream. So the re-request of data is not easy at the time of error detection. therefore EDAC algorithm is efficient. In this paper, we show a scheme, that is integration of graphic and dtv format signal for DTV monitor display. This paper also presents the efficiency error detection auto correction(EDAC) for conversion of graphics signal to DTV video signal. A presented EDAC algorithms use the modified hamming code for enhancing video quality and reliability. A EDAC algorithm of this paper can detect single error, double error, triple error and more error for preventing from incorrect correction. And it is not necessary an additional memory. In this paper The comparison between digital TV video signal and graphic signal, a EDAC algorithm and a design of conversion graphic signal to DTV signal with EDAC function in DTV system is described.

• 전기학회논문지
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• 제59권2호
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• 제어로봇시스템학회논문지
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• 제6권2호
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• 전기학회논문지
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• 제60권5호
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• pp.1036-1042
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• 2011

This paper presents an algorithm that conducts automatic memory scrubbing operated by dedicated hardwares. The proposed algorithm is designed so that it can scrub entire memory in a given scrub period, while minimally affecting the execution of flight softwares. The scrub controller is constructed in a form of state machines, which have two execution modes - normal mode and burst mode. The deadline event generator and period tick generator are designed in a separate way to support the behavior of the scrub controller. The proposed controller is implemented in VHDL code to validate its applicability. A simple version of the controller is also applied to mass memory modules used in STSAT-3.

• 항공우주기술
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• 제2권1호
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• pp.73-79
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• 2003

대부분의 위성 설계에서 우주 방사선에 의한 메모리 데이터 보호를 위해 오류정정회로를 내장하며, 동시에 오류의 누적을 방지하기 위해 주기적으로 메모리 내용을 읽는 알고리즘을 적용하고 있다. 소프트웨어에 의한 읽기 알고리즘을 적용하는 KOMPSAT 2호기의 경우 메모리 소자에 대한 방사능 영향 시험을 수행하지 않아 1호기에 비해 다소 큰 오류 가능성이 예측되었다. 소프트웨어 알고리즘 변경으로 읽기 작업을 하도록 결정하였으나 하드웨어에 의해 더 빠른 속도로 오류를 정정하도록 하는 방법도 연구되었다. 본 논문은 이러한 연구 결과로서, 최소 1.88분 정도의 주기로 1 Gbits의 메모리 영역을 읽음으로서 하드웨어만으로 메모리 내용을 보존할 수 있는 방법에 대하여 논의하였다.

• 전자공학회논문지SC
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• 제45권4호
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• pp.35-41
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• 2008

메모리 소자가 우주 환경에 노출되면 우주 방사능에 의해 메모리의 값이 변하는 SEU 현상이 발생한다. 이러한 현상에 대처하기 위하여 위성체에 사용되는 메모리는 필연적으로 오류 탐지 및 극복 기법을 탑재하고 있다. 본 논문에서는 과학기술위성 3호 대용량 메모리 유닛에서 채택하게 될 오류 탐지 및 극복 방식을 알아본다. 오류 극복을 위해 대용량 메모리를 RS(10,8) Reed-solomon 코드로 인코딩/디코딩했을 때 SEU에 의해 메모리의 데이터가 손상 받을 확률을 계산한다. 이 확률식을 기반으로 과학기술위성 3호가 직면할 수 있는 다양한 SEU 발생율에 대하여 그 확률 변화를 분석한다. 이것으로부터 과학기술위성 3호 대용량 메모리 유닛 설계의 중요한 요소 중의 하나인 메모리 인코딩/디코딩 주기를 결정하는데 이용하고자 한다.