• Journal of Advanced Navigation Technology
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• v.11 no.2
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• pp.170-176
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• 2007

In this paper, we improve performance for system when the carrier recovery signal is not perfect in the multipath mobile wireless communication fast fading channel based on DS-CDMA system. In the case, we use the phase estimation, diversity and adaptive FEC code technique in order to overcome this carrier phase error and mobile wireless fading. As a results in DS-CDMA system, we know that the appropriate use of diversity and adaptive FEC code technique reduced considerably performance degradation due to phase error.

• Proceedings of the KSR Conference
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• 2010.06a
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• pp.1075-1080
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• 2010

There have been lots of researches for High Performance Digital Signal Processing performance enhancement on a GPU(Graphic Processor Unit). These kinds of parallelizing can enable massive signal processing, so we can have advantage's of processing various of signal processing standards with GPU. In this paper we introduce Low Density Parity Check(LDPC) which is one of the Foward Error Correction(FEC). And we have achieved computational time reduce by using CUDA as a parallelizing scheme.

• Journal of Institute of Control, Robotics and Systems
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• v.12 no.8
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• pp.765-772
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• 2006

The L2 Civil Signal (L2CS) will be transmitted by modernized IIR(IIR-M), IIF and all subsequent GPS satellites. It contains two codes of different length; CM code contains 10,230chips, repeats every 20milliseconds and is modulated with message data, and CL code contains 767,250chips, repeats every 1.5second Z-count and has no data modulation. And the message data is encoded for Forward Error Correction(FEC). The long code length is useful for weak signal, but it also requires very long acquisition time. Therefore, the structure of GPS Ll/L2C Correlator and the fast acquisition scheme are proposed in this paper.

• Journal of the Institute of Convergence Signal Processing
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• v.7 no.3
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• pp.108-115
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• 2006

In this paper, a recognition algorithm of the straight line components of lane markings and an obstacle in the travelling lane region is proposed. This algorithm also involve the pitching error correction algorithm due to traveling vehicle's fluctuation. In order to reduce their error a practical road image modelling algorithm using V.F. model and camera calibration procedure are suggested to adapt the geometric variations. It is obtained the 3D world coordinate data by the 2D road images. In experimental test, we showed that this algorithm is available to recognize lane markings and an obstacle in the traveling lane.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.80-87
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• 2006

Recently, the distribution and using of the digital multimedia contents are easy by developing the internet application program and related technology. However, the digital signal is easily duplicated and the duplicates have the same quality compare with original digital signal. To solve this problem, there is the multimedia fingerprint which is studied for the protection of copyright. Fingerprinting scheme is a techniques which supports copyright protection to track redistributors of electronic inform on using cryptographic techniques. Only regular user can know the inserted fingerprint data in fingerprinting schemes differ from a symmetric/asymmetric scheme and the scheme guarantee an anonymous before recontributed data. In this paper, we present a new scheme which is the detection of colluded multimedia fingerprint by neural network. This proposed scheme is consists of the anti-collusion code generation and the neural network for the error correction. Anti-collusion code based on BIBD(Balanced Incomplete Block Design) was made 100% collusion code detection rate about the average linear collusion attack, and the hopfield neural network using (n,k)code designing for the error bits correction confirmed that can correct error within 2bits.

• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.1
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• pp.65-73
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• 2007

This paper presents an on-line correction method of current measurement errors for a pure-integration-based flux estimation down to 1-Hz stator frequency. An observer-based approach is taken as one possible solution of eliminating the dc offset and the negative sequence component of unbalanced gains in the synchronous coordinate. At the same time, the positive sequence component estimation is performed by creating an error signal between a motor model reference and an estimated q-axis rotor flux established by a permanent magnet (PM) in the synchronous coordinate. The compensator utilizes a PI controller that controls the error signal to zero. The proposed technique further contains a residual error compensator to completely eliminate miscellaneous disturbances in the estimated flux. The developed algorithm has been implemented on a 1.1-kW permanent magnet synchronous motor (PMSM) drive to confirm the effectiveness of the proposed scheme.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.69-78
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• 2001

This paper presents the design and FPGA implementation of a FLEX PSP(Protocol Signal Processor) for the portable high speed paging system. In this approach, two algorithms are newly proposed for implementing the PSP which provides capabilities of the maximum 6,400bps at speed, high-channel throughput, real time error correction and an effective frame search function. One is an accurate symbol synchronization algorithm which is applied for synchronizing the interleaved 4-level bit symbols which are received at input stage of A/D converter, and the other is a modified fast decoding algorithm which is provided for realizing double error correction of (31,21)BCH signal. The PSP is composed of six functional modules, and each module is modelled in VHDL(VHSIC Hardware Description Language). Both functional simulation and logic synthesis have performed for the proposed PSP through the use of Synopsys$^{TM}$ tools on a Axil-320 Workstation, and where Altera 10K libraries are used for logic synthesis. From logic synthesis, we can see that the number of gates is about 2,631. For FPGA implementation, timing simulation is performed by using Altera MAX+ PLUS II, and its results will be also given. The PSP which is implemented in 6 FPGA devices on a PCB has been verified by means of Logic Analyzer.r.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.4
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• pp.413-420
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• 2003

In this paper, the correction method of antenna beam direction errors is introduced which caused by frequency scan effect in active Phased may antenna for satellite communications. The antenna makes the beam directional error from frequency scan effect when it has dual beam may structure with asymmetrical series connection, their frequencies are different and for from each other, their 3dB beamwidth is narrow, and scan range is wide. By proposed equations, estimated beam direction error angles can be calculated and active phase shifter control values also can be calculated to compensate them. In this paper, the active phased array antenna system was fabricated to measure beam direction errors both before and after correction, which has dual beam from 32${\times}$4 main level array and 4${\times}$2 second level array, frequency deviation 500 MHz max.(6.7 %) at 7.25 GHz∼7.75 GHz ranges, 0$^{\circ}$∼${\pm}$35$^{\circ}$nm ranges, and 35.6 dBi gain with 2.2$^{\circ}$3 dB beam width. Its beam direction error by frequency san effect which was 2.5$^{\circ}$max., was reduced to 0.2$^{\circ}$max. after correction. This was 7 dB improvement of signal loss. The active phased array antenna can accurately track the target satellite for communications by this proposed correction method.

• The Journal of Information Technology
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• v.7 no.3
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• pp.37-45
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• 2004

The representative communication method which is applied in the low-speed power line communication modem with 60bps is single carrier method. It has been used mainly for the control. The single carrier method is very sensitive to a power line communication channel environment. Specially, the severe attenuation of the transmission signal according to the notch characteristics of channel becomes the main cause of communication error. Domestic power line channel environment has this notable feature. In this paper, we implemented the low-speed power line communication system which used the chirp signal method to be strong in notch and noise characteristics. In this research, we proposed the method which transmits 1- '1 Unit symbol Chirp signal' with a 100${\mu}s$ time within 1ms for 1 bit. Also it applied for the Convolution code for an error correction and the Manchester code for a collision perception and an error detection. It used the method which uses the bit correlator for signal detection in the receiver parts. We confirmed that the communication method of the chirp method has a excellent performance compared to single carrier methods with a result of experiment of the low-speed power line communication system with the 60bps.