• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.465-472
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• 2013

This paper presents a low-complexity triple-error-correcting parallel Bose-Chaudhuri-Hocquenghem (BCH) decoder architecture and its efficient design techniques. A novel modified step-by-step (m-SBS) decoding algorithm, which significantly reduces computational complexity, is proposed for the parallel BCH decoder. In addition, a determinant calculator and a error locator are proposed to reduce hardware complexity. Specifically, a sharing syndrome factor calculator and a self-error detection scheme are proposed. The multi-channel multi-parallel BCH decoder using the proposed m-SBS algorithm and design techniques have considerably less hardware complexity and latency than those using a conventional algorithms. For a 16-channel 4-parallel (1020, 990) BCH decoder over GF($2^{12}$), the proposed design can lead to a reduction in complexity of at least 23 % compared to conventional architecttures.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.195-204
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• 2007

The cyclic redundancy check(CRC) code used to decide retransmission request in hybrid automatic repeat request(HRAQ) system can also be used to stop iterative decoding of turbo code if it is used as an error correcting code(ECC) of HARQ system. Thus a scheme to use CRC code for both iteration stop and repeat request in the HARQ system with turbo code based on the standard of cdma 2000 system is proposed in this paper. At first, the optimum CRC code which has the minimum length without performance degradation due to undetected errors is found. And the most appropriate turbo encoder structure is also suggested. As results, it is shown that at least 32-bit CRC code should be used and a turbo code with 3 constituent encoders is considered to be the most appropriate one.

• Journal of IKEEE
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• v.21 no.2
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• pp.130-135
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• 2017

Normally, in data transmission, extra parity bits are added to the input message which were derived from its input and a pre-defined algorithm. The same algorithm is used by the receiver to check the consistency of the delivered information, to determine if it is corrupted or not. It recovers and compares the received information, to provide matching and correcting the corrupted transmitted bits if there is any. This paper aims the following objectives: to use an alternative error detection-correction method, to lessens both the fixed number of the required redundancy bits 'r' in cyclic redundancy checking (CRC) because of the required polynomial generator and the overhead of interspersing the r in Hamming code. The experimental results were synthesized using Xilinx Virtex-5 FPGA and showed a significant increase in both the transmission rate and detection of random errors. Moreover, this proposal can be a better option for detecting and correcting errors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.7
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• pp.1787-1802
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• 1996

In this paper, the performance for FH/CPFSK system with limiter-discriminator detection and integrage-and-dump post-detection filtering under thermal noie, partial-band noise jamming and rayleigh fading have been analyzed. The method of hard-decision diversity of which the transmitter repeated L times on different hops for each data symbol in a way to mutigate the effects of the jamming has been applied, and the receiver has been combined the L chips. Also, error-correcting code have been applied for improving performance of system. The thermal noise and partial-band noise jamming, intersymbol interference for all eight of the possible adjacent bit data patterns, and FM noise click for evaluating systems have been considered. Also optimum parameters to improve performance of FH/CPFSK system have been obtained and validities have been proved through computer simulation.

• Communications of the Korean Mathematical Society
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• v.20 no.2
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• pp.405-409
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• 2005

In [1], Sharma and Goel obtained a bound for random error correcting codes with Lee weight considerations. The purpose of this paper is to first point out a discrepancy in this result and then give a correct version of the same, improving upon the bound tremendously.

• Journal of Electrical Engineering and information Science
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• v.1 no.1
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• pp.23-28
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• 1996

In this series of two papers, adaptive code rate change schemes in DS-SSMA systems are proposed. In the proposed schemes the error correcting code rate is changed according to the channel states. Two channel states having significant effects on the bit error probability are considered: one is the effective number of users considered in Part 1, and the other is the fading environment considered in Part 2. These channel states are estimated based on retransmission requests. The criterion for the change of the code rate is to maximize the throughput under given error bound. Simulation results show that we can transmit maximum amount of information if we change the code rate based on the channel states.

• Proceedings of the KIEE Conference
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• 1985.07a
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• pp.254-256
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• 1985

• Bulletin of the Korean Mathematical Society
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• v.52 no.3
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• pp.809-823
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• 2015

This paper is devoted to presenting a MacWilliams type identity for m-spotty RT weight enumerators of byte error control codes over finite commutative Frobenius rings, which can be used to determine the error-detecting and error-correcting capabilities of a code. This provides the relation between the m-spotty RT weight enumerator of the code and that of the dual code. We conclude the paper by giving three illustrations of the results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.9
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• pp.1180-1186
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• 2020

One of the Embedded systems Tiny Processing Unit (TPU) usually acts in harsh environments like external shock or insufficient power. In these cases, data could be polluted, and cause critical problems. As a solution to data pollution, many embedded systems are using Error Correcting Code (ECC) to protect and restore data. However, ECC processing in TPU increases the overall processing time by increasing the time of instruction fetch which is the bottleneck. In this paper, we propose an architecture of parallelized ECC block to the reduce bottleneck of TPU. The proposed architecture results in the reduction of time 10% compared to the original model, although memory usage increased slightly. The test is evaluated with a matrix product that has various instructions. TPU with proposed parallelized ECC block shows 7% faster than the original TPU with ECC and was able to perform the proposed test accurately.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.273-276
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• 2000

Recently, Turbo code has been considered for channel coding in IMT-2000(International Mobile Telecommunication-2000) system, because it offers better error correcting capability than the traditional convolution/viterbi coding . In this paper, a turbo code decoder for speech transmission in IMT-2000 system with frame size 192 bits, constrait length K=3, generator polynomials G(5,7) and code rate R=1/3 is designed using SOVA(Soft Output Viterbi Algorithm) and block interleaver