• Progress in Medical Physics
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• v.2 no.2
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• pp.175-182
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• 1991

A newly derived O$_2$ Saturation Model which can be adapted to the design and study of Artificial Lung and Blood Gas Calculator etc. is introduced on the basis of Electrical Equivalent Circuits. The presented 4 stage and 2 stage RC circuits have good correlatons with actual chemical reactions of Hemoglobin and Oxygen. However, from results of computer simulations, 2 stage equivalent model is more accurate than 4 stage and conventional O$_2$ saturation models.

• Journal of Advanced Marine Engineering and Technology
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• v.22 no.5
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• pp.617-625
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• 1998

A passive energy recovery snubber for high-power-factor boost rectifier, in which the main switch is implemented with a MOSFET, is described in terms of the equivalent circuits that are operational during turn-on and turn-off sequences. These equivalent circuits are analyzed so that the overshoot voltage across the main switch, the snubber current, and the turn-off transition time can be predicted analytically. From these results, the normalized overshoot voltage is reduced to 1 as $_W2T_on$ varies from zero to $\pi$/2, and then it is fIxed at 1 for $_W2T_on$> $\pi$/2. The peak snubber inductor current is directly proportional to the input current. The turn-offtransition time wltoffvaries from 0 to 2.57, depending on $_W2T_on$. The main switch combined with proposed snubber can be turned on with zero current and turned off at limited voltage stress. The high-power-factor boost rectifier with proposed snubber is implemented, and the experimental results are presented to confirm the validity of proposed snubber.

• Proceedings of the KIPE Conference
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• 1998.10a
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• pp.668-676
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• 1998

A passive energy recovery snubber for high-power-factor boost rectifier, in which the main switch is described in terms of the equivalent circuits that are operational during turn-on and turn-off sequences. These equivalent circuits are analyzed so that the overshoot voltage across the main switch, the snubber current, and the turn-off transition time can be predicted analytically. The main switch combined with proposed snubber can be turned on with zero current and turned off at limited voltage stress. The high-power-factor boost rectifier with proposed snubber is implemented, and the experimental results are presented to confirm the validity of proposed snubber.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.11
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• pp.1967-1971
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• 2007

In this paper, we verified basic forms and equivalent circuits of spiral inductors and various kinds of parasitics of equivalent circuits by using HFSS and Nexxim program that were 3-D EM analysis tools, and fabrication on-chip spiral inductors using Hynix's 0.25um 1-poly and 5-metal CMOS process. Comparing with PGS(patterned ground shield) and NPGS(non patterned ground shield) of spiral inductors of 3.5 turn, 4.5 turn and 5.5 turn, etc, the application of PGS could improve maximum Q value by 8-12%.

• Journal of Power Electronics
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• v.2 no.2
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• pp.139-145
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• 2002

Because conventional switching converters have been usually using unbalanced circuit topologies, parasitice between the drain/collertor of an active switch and frame ground through its heat sink may generate the commom-mode conducted noise. We have proposed a balanced switching converter circuit, whitch is an effective way to reduce the commom-mode converter version of the balanced switching converter was presented and the mechanism of the commom-mode noise reduction was explained using equivalent circuits. This paper extends the concept of the balanced switch converter circuit and presents a buck-boost converter version of the blanced switching converter. The feature of common-mode niose reduction is confirmed by experimental resuits and the mechanisem of the commom-mode niose reduction is explained using equivalent circuits.

• Journal of the Korean Institute of Telematics and Electronics
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• v.10 no.6
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• pp.11-24
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• 1973

A new simple technique for 2-terminal negative resistance cireait analysis and synthesis is developed, by using the equivalent e.m.f. defined as a function of input lotage or current variation. The technique is applied to design 2-terminal junction transistor negative resistance circuits based on the parameter control method. Modeling circuits for SCR, GTO-SCR and SSS are also derived from the proposed transistor negative resistance circuits, and the merits of the modeling circuits are discussed.

• Journal of Industrial Technology
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• v.13
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• pp.59-69
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• 1993

Using two current conveyors with the grounded capacitors and resistors, this paper proposed equivalent circuits which can realize the floating L and the floating FDNR. To find out their characteristics, we experiment with these circuits instead of the floating L of the low-pass filter and the floating FDNR of the high-pass filter respectively. Comparing theoretical values with experimental ones, values of the proposed floating L represent the error of 5 percents in the frequency range from 5 KHz to 25 KHz, and values of the floating FDNR represent the error of 5 percents in the range from 8 KHz to 25 KHz. So the proposed floating L and the FDNR circuits are expected to be implemented with current conveyors of an IC.

• Publications of The Korean Astronomical Society
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• v.13 no.1 s.14
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• pp.123-128
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• 1998

The Blandford-Znajek process, which extracts the rotational energy of the supermassive black hole at the center of an active galactic nucleus, is now well explained and educated through the electronic circuit analysis established by Macdonald and Thorne. The Macdonald-Thorne circuits consist of the batteries and resistances of the central black hole and the astrophysical region around the accretion disk. In this letter we will consider the possibility whether we can connect coils and condensers in such circuits or not. If possible, that may explain a sudden corona-phenomenon in an active galactic nucleus. We conclude that a flash of order $\~5\times10^{40}\;ergs\;s^{-1}$ can occur around a $\~10^9M_\bigodot$ black hole through this process.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.3
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• pp.11-22
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• 1997

This paper presents the design and implementation of an efficient algorithm for detecting untestable paths in multi-level circuits. Transforming multi-level circuit into a multiplexor-based one through BDD(binary decision diagram)construction, the proposed algorithm detects untestable paths in the transformed circuits. By constructing ENF (equivalent normal form) only for reconvergent paths, the proposed system detects and removes untestable paths efficiently in terms of the run-time and memory usage. Experimental results for MCNC/ISCAS benchmark circuits show that the system efficiently detects and removes untestable paths. The run-time and memory usage have been reduced by 37.7% and 60/9%, respectively, comapred to the previous methods.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2011.06a
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• pp.194-194
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• 2011