• Proceedings of the KIEE Conference
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• 2004.07c
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• pp.1585-1587
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• 2004

이중 에피층 구조를 가지는 SOI(Silicon-On-Insulator) LIGBT(Lateral Insulated Gate Bipolar Transistor)의 에피층 두께 변화에 따른 항복전압 특성을 분석하였다. 제안된 소자는 전하보상효과를 얻기 위해 n/p-epi의 이중 에피층 구조를 사용하였으며, 에피층 전체에 걸쳐서 전류가 흐를 수 있도록 하기 위해 trenched anode구조를 채택하였다. 본 논문에서는 n/p-epi층의 농도를 고정시킨 후 각각의 epi층의 두께를 변화시켜가며 simulation을 수행하였을 때 항복전압의 변화 및 표면과 epi층에서의 전계분포변화를 분석하였다.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.74-77
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• 2002

In this paper we present a novel temperature compensated Hall effect power IC for accurate operation of wide temperature and high current drive of the motor coil. In order to compensate the temperature dependence of Hall sensitivity with negative temperature coefficient(TC), the differential amplifier has the gain consisted of epi-layer resistor with positive TC. The material of Hall device and epi-resistor is epi-layer with the same mobility. The variation of Hall sensitivity is -38% at 150$^{\circ}C$ and 88% at - 40$^{\circ}C$. But the operating point(B$\sub$op/) and release point(B$\sub$RP/) of the Hall power IC are within ${\pm}$25%. The experimental results show very stable and accurate performance over wide temperature range of -40$^{\circ}C$ to 125$^{\circ}C$.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.7
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• pp.134-142
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• 1996

The epi-CoSi$_{2}$ layer was formed by alloying a Co(120$\AA$)/Ti(50$\AA$) bilayer. In addition, the ultra shallow p$^{+}$n junction of which depth is about not more than 40nm at the background concentration, 10$^{18}$atoms/cm$^{3}$ could be formed by annealing (RTA-II) the ion implanted epi-silicide. When the temperature of RTA-I is as low as possible and that of RTA-II is moderate, the p$^{+}$n junction that has low leakage current and stable epi-silicide layer could be obtained. That is, when th econdition of TRA-I was 900$^{\circ}C$/20sec and that of RTA-II was 900$^{\circ}C$/10sec, the reverse leakage current was as high as 11.3$\mu$A/cm$^{2}$ at -5V. The surface of CoSi$_{2}$ appeared considerably rough. However, when the conditon of RTA-I was 800$^{\circ}C$/20sec or 700$^{\circ}C$/20sec, the leakage currents were as low as 8.3nA/cm$^{2}$ and 9.3nA/cm$^{2}$, respectively and also the surfaces appeared very uniform.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.288-291
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• 2004

Due to the charge compensation effect, SOI(Silicon-On-Insulator) LIGBT with dual-epi layer have been found to exhibit both low forward voltage drop and high static breakdown voltage. In this paper, electrical characteristics of the SOI LIGBT with dual-epi structure is presented. Trenched anode structure is employed to obtain uniform current flowlines and shorted anode structure also employed to prevent the fast latch-up. Latching current density of the proposed LIGBT with $T_1=T_2=2.5{\mu}m,\;N_1=7{\times}10^{15}/cm^3,\;N_2=3{\times}10^{15}/cm^3$ is $800A/cm^2$ and breakdown voltage is 125V while latching current density and breakdown voltage of the conventional LIGBT is $700A/cm^2$ and 55V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.63-63
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• 2009

In this work, we demonstrate 800V 4H-SiC power DMOSFETs with several structural alterations to observe static DC characteristics, such as a threshold voltage ($V_{TH}$) and a figure of merit ($V_B^2/R_{SP,ON}$). To optimize the static DC characteristics, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. Design parameters are optimized using 2D numerical simulations and the 4H-SiC DMOSFET structure results in high figure of merit ($V_B^2/R_{SP,ON}$>~$340MW/cm^2$) for a power MOSFET in $V_B{\sim}1200V$ range.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.8
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• pp.637-640
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• 2009

In this work, we demonstrate 800 V 4H-SiC power DMOSFETs with several structural alterations to obtain a low threshold voltage ($V_{TH}$) and a high figure of merit ($V_B\;^2/R_{SP,ON}$), To optimize the device performance, we consider four design parameters; (a) the doping concentration ($N_{CSL}$) of current spreading layer (CSL) beneath the p-base region, (b) the thickness of p-base ($t_{BASE}$), (c) the doping concentration ($N_J$) and width ($W_J$) of a JFET region, (d) the doping concentration ($N_{EPI}$) and thickness ($t_{EPI}$) of epi-layer. These parameters are optimized using 2D numerical simulation and the 4H-SiC DMOSFET structure results in a threshold voltage ($V_{TH}$) below $^{\sim}$3.8 V, and high figure of merit ($V_B\;^2/R_{SP,ON}$>$^{\sim}$200 $MW/cm^2$) for a power MOSFET in $V_B\;^{\sim}$800 V range.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.110-111
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• 2006

이중 에피층을 가지는 SOI (Silicon-On-Insulator) RESURF(REduced SURface Field) LIGBT(Lateral Insulated Gate Bipolar Transistor) 소자의 에피층 두께에 따른 항복전압 특성을 분석하였다. 이중 에 피층 구조를 가지는 SOI RESURF LIGBT 소자는 전하보상효과를 얻기 위해 기존 LIGBT 소자의 n 에피로 된 영역을 n/p 에피층의 이중 구조로 변경한 소자로 n/p 에피층 영역내의 전하간 상호작용에 의해 에피 영역 전체가 공핍됨으로써 높은 에피 영역농도에서도 높은 항복전압을 얻을 수 있는 소자이다. 본 논문에서는 LIGBT 에피층의 전체 두께와 농도를 고정한 상태에서 n/p 에피층의 두께가 변하는 경우에 항복전압 특성의 변화에 대해 simulation을 통해 분석하였다.

• 전기의세계
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• v.26 no.5
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• pp.83-89
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• 1977

This paper described the minority carrier lifetime in Si epitaxial layer, and also the voltage (V) versus current (I) characteristics of high resistivity Si epitaxial layer0substrate junction. The measured lifetime in Si epi-layer was much shorter than in bulk, and the temperature dependence of lifetime was found to agree well with Shockley-Read model of recombination which applies to high resistivity n-type materials. The V-I curve showed; an ohmic region (I.var.V), a sublinear region (I.var.V$^{1}$2/), a space charge limited current region (I.var.V$^{2}$), and finally a negative resistance region. We investigated these phenomena by the theory of the relaxation semiconductor.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2015.10a
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• pp.1121-1124
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• 2015

In this paper, we propose and demonstrate an optimal design of wideband pulsed gamma-ray detectors. Pulsed gamma-ray detectors are designed to operate in a dose rate of $1{\times}10^6{\sim}1{\times}10^8rad(Si)/s$. The input parameter was derived based on the energy ratio of pulse gamma-ray spectrum and the time of the energy. The sensor output current was calculated based on the dose rate control circuit. Using the N-type Epi Wafer, the optimum condition detection sensor was designed based on TCAD. The simulation results show that the optimal Epi layer thickness is 45um when applied voltage 3.3V. The doping concentrations are as follows : N-type is an Arsenic as $1{\times}10^{19}/cm^3$, P-type is a Boron as $1{\times}10^{19}/cm^3$ and Epi layer is Phosphorus as $3.4{\times}10^{12}/cm^3$. Pulse gamma-ray detector diameter is the 1.3mm.

• 전자공학회논문지 IE
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• v.48 no.2
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• pp.1-5
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• 2011

The epitaxial GaN layer of $120{\mu}m$ ~ $300{\mu}m$ thickness with a stripe Ti mask pattern is performed by hydride vapor phase epitaxy(HVPE). Ti strpie mask pattern is deposited by DC magnetron sputter on GaN epitaxial layer of $3{\mu}m$ thickness is grown by hydride vapor phase epitaxy(HVPE). Void are observed at point of Ti mask pattern when GaN layer is investigated by scanning electron microscope. The Crack of GaN layer is observed according to void when it is grown more thick GaN layer. The full width at half maximum of peak which is measured by X-ray diffraction is about 188 arcsec. It is not affected its crystallization by Ti meterial when GaN layer is overgrown on Ti stripe mask pattern according as it is measure FWHM of overgrowth GaN using Ti material against FWHM of first growth GaN epitaxial layer.