• Journal of the Korean Society of Earth Science Education
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• v.13 no.1
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• pp.121-133
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• 2020

This study proposes a lesson design framework to design a science and engineering integrated lesson in a meaningful and easy way based on engineering design, which is the core feature of STEM education. The science and engineering integrated lesson design framework is developed based on the analysis of domestic and foreign theoretical and practical research papers and expert discussion on science and engineering integrated education as well as the feedbacks from science teachers. The science and engineering integrated lesson design framework uses engineering design as the main pedagogical method. The framework includes the core elements of the engineering integrated lesson suggested in previous studies and the achievement level of each grade group suggested in NGSS and provides a way for teachers to easily introduce engineering design into science classes. In addition, the framework developed in this study complements the shortcomings of the complicated Korean STEAM education framework. It can also provide specific guidance to in-service teachers as well as pre-service teachers to easily understand and apply engineering design and problem solving processes to science and engineering integrated lessons.

• Journal of Practical Engineering Education
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• v.11 no.2
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• pp.151-158
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• 2019

As the competitiveness of university education and the demand for innovation have increased, a flexible educational system considering the characteristics of universities has become necessary. In particular, in the case of K-university, the intensive semester of Graduation Design, which dramatically improves the educational purpose, content, evaluation, and operation method of the graduate design subject, in order to cultivate a creative engineer capable of actively responding to technological change and solving practical problems. K University's intensive semester of graduation design was operated in two majors in the first semester in 2018, and three majors in the first semester in 2019. A result of survey on the status and effectiveness of intensive semester of graduation design was conducted for participating instructors and students, it was shown that the purpose of introducing intensive semester of graduation design, such as improving the instruction time, the quality of the graduation work and cultivating the competency of the student, was effective.

• Journal of IKEEE
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• v.27 no.4
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• pp.683-686
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• 2023

In this paper, we designed a Delayed Dual Core Lock-Step (D-DCLS) processor where two cores operate same instructions with delay and the result is compared to mitigate soft errors and common mode failures in automotive electronic systems. Because D-DCLS does not know which core an error occurred in, each core must be recovered to the point before the error occurred, but complex hardware modifications are required to return all intermediate values on the pipeline stage. In this paper, in order for easy hardware implementation, all register values are saved to a buffer whenever a branch instruction is executed. When an error is detected, the saved register values are automatically restored, and then 'BX LR' instruction is executed to return to the last branch point. The proposed D-DCLS processor was designed using Verilog HDL and was confirmed to continue normal operation after automatically recovering error.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.2 s.344
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• pp.51-59
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• 2006

Von Neumann architecture suffers from the interface between the central processing unit and the memory, which is called 'Von Neumann bottleneck' In this paper, we propose a scalable general-purpose associative processor (AP) based on content-addressable memory (CAM) which solves this problem and is suitable for the search-oriented applications. We propose an efficient instruction set and a structural scalability to extend for larger applications. We define twelve instructions and provide some reduced instructions to speed up which execute two instructions in a single instruction cycle. The proposed AP performs in a bit-serial, word-parallel fashion and can be considered as a 32-bit general-purpose parallel processor with a massively parallel SIMD structure. We design and simulate a maximum/minumum search greater-than/less-than search, and parallel addition to verify the proposed architecture. The algorithms are executed in a constant time O(k) regardless of the number of input data.

• ETRI Journal
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• v.25 no.5
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• pp.337-344
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• 2003

In this paper, we introduce a fully synthesizable 32-bit embedded microprocessor core called the AE32000B. The AE32000B core is based on the extendable instruction set computer architecture, so it has high code density and a low memory access rate. In order to improve the performance of the core, we developed and adopted various design options, including the load extension register instruction (LERI) folding unit, a high performance multiply and accumulate (MAC) unit, various DSP units, and an efficient coprocessor interface. The instructions per cycle count of the Dhrystone 2.1 benchmark for the designed core is about 0.86. We verified the synthesizability and the area and time performances of our design using two CMOS standard cell libraries: a 0.35-${\mu}m$ library and a 0.18-${\mu}m$ library. With the 0.35-${\mu}m$ library, the core can be synthesized with about 47,000 gates and operate at 70 MHz or higher, while it can be synthesized with about 53,000 gates and operate at 120 MHz or higher with the 0.18-${\mu}m$ library.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.585-588
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• 2005

The Presence Agent Server receives user's presence information via PUBLISH request message and let subscribers to know that information. IMPP client has a functions for PUA(presence user agent) as a base operational entity. In some circumstance, the client has both pua and pa logical entities. However presence agent server has take part only of PA. In this paper, we describes the design and implementation that contains modules based configurations and approaches for presence agent server. Also, we describe how we handle each events and database API instruction set.

• The KIPS Transactions:PartD
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• v.8D no.6
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• pp.673-680
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• 2001

When the developers develop the software, the cost and time of the software development can be reduced by using blocks that are implemented previously. We call these implemented blocks components. In the early stage of Web-based Instruction, it didn't gain preference in spite of it's benefit of convenience. The main reason is, I think, the lack of generality at the education system which eventually results in unsatisfactory facilities compared with the requirement of teachers and students. And the early systems don't make good use of the plenty data in distributed environment, and don't show so good reliablity due to lack of systematic design and development. In this paper, we suggest WBI developing technology using the concept of WBSE. WBI developing is consist of component of pre-developed education software, integration of component using its reusability, and production of more requirement-satisfactory education software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.54-60
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• 2006

In order to test the board with IEEE 1149.1 boundary scan design, the test sequence must be applied as the bit stream However it is very tedious job to generate the test bit sequence since it requires the complete hlowledge about the 1149.1. This fuper introduces a convenient PCI/USB interface controller, named as Test-Ready PCI (TRPCI) ard Test-Ready USB (TRUSB). Test Bus Controller has been developed by TI and Lucent aiming to generate the test bit stream as an instruction level, thus even the novice test engineer can easily generate the test sequence.

• Journal of Forest and Environmental Science
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• v.22 no.1
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• pp.50-57
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• 2006

The design instruction put in the wood structure construction manual of forest engineering works issued in Japan in 2004 is composed of the introduction, the use and characteristic of wood, investigation, planning, design, and etc. We analyzed planing and construction. By the results, the contents for the design are shown about applied woody conditions and deterioration, structure, selection of tree, the standardization of the size displays in wood, safety and examination of intensity, intensity of wood, the ranges of wood size allowance, and etc. With respect to the construction of wood structure, there are detailed descriptions regarding security of wood quality, confirmation of wood quality by preservative treatment and security methods of function in wood structure, the regular investigation method, the qualitative standard criterion and the quantitative examination method on the deterioration of wood.

• Journal of Engineering Education Research
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• v.24 no.5
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• pp.38-45
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• 2021

The CanSat was designed as an educational satellite simulation program that implements the overall system of the satellite such as the command processing unit, the communication unit, and the power unit in a structure of the size of a can. In particular, the training effect is very excellent because the trainee can learn a process similar to the actual satellite development process by designing, manufacturing, testing, and launching. Republic of Korea Air Force Academy has been using the CanSat production kit used by the domestic can satellite contest experience department for education, but since it was produced based on PCB, it was impossible to show creativity and operation was restricted even with small mistakes. In this paper, we analyze the existing CanSat kit and propose a new educational CanSat kit that can be used in creative engineering design and practice subjects that will be reorganized into a regular course from 2021, and a lesson plan. In conclusion, by using the proposed CanSat kit for lectures, it is possible to achieve educational purposes and effects, improve lecture satisfaction, and provide stable instruction.