• Proceedings of the IEEK Conference
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• 2003.07d
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• pp.1685-1688
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• 2003

The modem multimedia applications which are video Processor, video conference or video phone and so forth require real time processing. Because of a large amount of image data, those require high compression performance. In this paper, the proposed image processing encoder was designed by using wavelet transform encoding. The proposed filter block can process image data on tile high speed because of composing individual function blocks by parallel and compute both highpass and lowpass coefficient in the same clock cycle. When image data is decomposed into multiresolution, the proposed scheme needs external memory and controller to save intermediate results and it can operate within 33㎒.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1340-1345
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• 2001

In this paper, we proposed the method computing the optimal solution of Optical Flow(OF) representing the moving information of moving object and improving the operating speed. In order to do that, we computed the optimal solution of OF using the Combinatorial Hough Transform(CHT) and Voting accumulation and simply searched the moving object compared to conventional method.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.722-725
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• 2008

In this paper, we propose a new approach for fast generation of CGHs of a 3-D object by using the run-length encoding and N-LUT methods. In this approach, object points to be involved in calculation of the CGH pattern can be dramatically reduced and as a result a significant increase of computational speed can be obtained.

• Journal of Electrical Engineering and Technology
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• v.3 no.3
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.498-503
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• 2009

As for Hadamard Transform, because the calculation time of this transform is slower than Discrete Cosine Transform (DCT) and Fast Fourier Transform (FFT), the effectiveness and the practicality are insufficient. Then, the computational complexity can be decreased by using the butterfly operation as well as FFT. We composed calculation time of FFT with that of Fast Complex Hadamard Transform by constructing the algorithm of Fast Complex Hadamard Transform. They are indirect conversions using program of complex number calculation, and immediate calculations. We compared calculation time of them with that of FFT. As a result, the reducing the calculation time of the Complex Hadamard Transform is achieved. As for the computational complexity and calculation time, the result that quadrinomial Fast Complex Hadamard Transform that don't use program of complex number calculation decrease more than FFT was obtained.

• Journal of Broadcast Engineering
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• v.27 no.7
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• pp.1011-1020
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• 2022

Recent high-performance panoptic segmentation models are based on transformer architectures. However, transformer-based panoptic segmentation methods are basically slower than convolution-based methods, since the attention mechanism in the transformer requires quadratic complexity w.r.t. image resolution. Also, sine and cosine computation for positional embedding in the transformer also yields a bottleneck for computation time. To address these problems, we adopt three modules to speed up the inference runtime of the transformer-based panoptic segmentation. First, we perform channel-level reduction using depth-wise separable convolution for inputs of the transformer decoder. Second, we replace sine and cosine-based positional encoding with convolution operations, called conv-embedding. We also apply a separable self-attention to the transformer encoder to lower quadratic complexity to linear one for numbers of image pixels. As result, the proposed model achieves 44% faster frame per second than baseline on ADE20K panoptic validation dataset, when we use all three modules.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.54-61
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• 2008

This paper presents a new TIQ based CMOS flash 6-bit ADC to process digital signal in real time. In order to improve the conversion speed of ADC by designing new logic or layout of ADC circuits, a new design method is proposed in encoding logic circuits. The proposed encoding circuits convert analog input into digitally encoded double base number system(DBNS), which uses two bases unlike the normal binary representation scheme. The DBNS adopts binary and ternary radix to enhance digital arithmetic processing capability. In the DBNS, the addition and multiplication can be processed with just shift operations only. Finding near canonical representation is the most important work in general DBNS. But the main disadvantage of DBNS representation in ADC is the fan-in problem. Thus, an equal distribution algorithm is developed to solve the fan-in problem after assignment the prime numbers first. The conversion speed of simulation result was 1.6 GSPS, at 1.8V power with the Magna $0.18{\mu}m$ CMOS process, and the maximum power consumption was 38.71mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12B
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• pp.1407-1417
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• 2009

We propose a e-document management system that can provide segmented page information on a document according to different levels of authority from access control environment. The proposed system creates hierarchy identifier using a one-way hash chain and therefore does not need to own key information for all users as in existing system. Also by creating group keys by compounding hash chain hierarchy identifier with randomly formed group identifier, the system can flexibly respond to dynamic changes from group member movements while at the same time resolving the problems of key formation and management in document encoding technique using symmetric key for each page. Lastly as a result of comparative analysis through an experiment with existing e-document management systems, the proposed system showed superiority in the efficiency of encoding and decoding document and the speed of encoding and decoding by the pages.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.3
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• pp.179-187
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• 2000

Fractal theory has strengths such as high compression rate and fast decoding time in application to image compression, but it suffers from long comparison time necessary for finding an optimally similar domain block in the encoding stage. This paper proposes a neural network based block classifier which enhances the encoding time significantly by classifying domain blocks into 4 patterns and searching only those blocks having the same pattern with the range block to be encoded. Size of a block is differently determined depending on the image complexity of the block. The proposed algorithm has been tested with three different images having various featrues. The experimental results have shown that the proposed algorithm enhances the compression time by 40% on average compared to the conventional fractal encoding algorithms, while maintaining allowable image qualify of PSNR 30 dB.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.112-120
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• 2013

In this paper, we propose high-performance H.264/AVC CAVLC encoder for UD video real time processing. Statistical values are obtained in one cycle through the parallel arithmetic and logical operations, using non-zero bit stream which represents zero coefficient or non-zero coefficient. To encode codeword per one cycle, we remove recursive operation in level encoding through parallel comparison for coefficient and escape value. In oder to implement high-speed circuit, proposed CAVLC encoder is designed in two-stage {statical scan, codeword encoding} pipeline. Reducing the encoding table, the arithmetic unit is used to encode non-coefficient and to calculate the codeword. The proposed architecture was simulated in 0.13um standard cell library. The gate count is 33.4Kgates. The architecture can support Ultra Definition Video ($3840{\times}2160$) at 100 frames per second by running at 100MHz.