• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.2
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• pp.439-446
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• 2011

In this paper, we proposed and implemented a dedicated hardware for Huffman coding which is a method of entropy coding to use compressing multimedia data with video coding. The proposed Huffman codec consists Huffman encoder and decoder. The Huffman encoder converts symbols to Huffman codes using look-up table. The Huffman code which has a variable length is packetized to a data format with 32 bits in data packeting block and then sequentially output in unit of a frame. The Huffman decoder converts serial bitstream to original symbols without buffering using FSM(finite state machine) which has a tree structure. The proposed hardware has a flexible operational property to program encoding and decoding hardware, so it can operate various Huffman coding. The implemented hardware was implemented in Cyclone III FPGA of Altera Inc., and it uses 3725 LUTs in the operational frequency of 365MHz

• Journal of The Korean Association of Information Education
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• v.20 no.4
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• pp.333-340
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• 2016

When elementary students write their own sentences, it is often educationally beneficial to compare them with other people's similar sentences. However, it is impractical for use in most classrooms, because it is burdensome for teachers to look up all of the sentences written by students. To cope with this problem, we propose a novel approach for automatic selection of similar sentences based on a three-step process: 1) extracting the subword units from the word-level sentences, 2) training the model with the encoder-decoder architecture, and 3) using the approximate k-nearest neighbor search algorithm to find the similar sentences. Experimental results show that the proposed approach achieves the accuracy of 75% for our test data.

• Journal of Ocean Engineering and Technology
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• v.35 no.4
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• pp.287-295
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• 2021

This paper describes a recurrent neural network (RNN) for the fault classification of a blade pitch system of a spar-type floating wind turbine. An artificial neural network (ANN) can effectively recognize multiple faults of a system and build a training model with training data for decision-making. The ANN comprises an encoder and a decoder. The encoder uses a gated recurrent unit, which is a recurrent neural network, for dimensionality reduction of the input data. The decoder uses a multilayer perceptron (MLP) for diagnosis decision-making. To create data, we use a wind turbine simulator that enables fully coupled nonlinear time-domain numerical simulations of offshore wind turbines considering six fault types including biases and fixed outputs in pitch sensors and excessive friction, slit lock, incorrect voltage, and short circuits in actuators. The input data are time-series data collected by two sensors and two control inputs under the condition that of one fault of the six types occurs. A gated recurrent unit (GRU) that is one of the RNNs classifies the suggested faults of the blade pitch system. The performance of fault classification based on the gate recurrent unit is evaluated by a test procedure, and the results indicate that the proposed scheme works effectively. The proposed ANN shows a 1.4% improvement in its performance compared to an MLP-based approach.

• The KIPS Transactions:PartC
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• v.10C no.2
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• pp.233-240
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• 2003

In this paper, an improved architecture of turbo codec for IMT-2000 is proposed. The encoder consists of an interleaver using an on-the-fly type address generator and a modified shift register instead of an external RAM, and the decoder uses a decreased number of RAM. The proposed architecture is simulated with C/VHDL languages, where BER (bit-error-rate) performances are generally in agreement with previous data by varying interaction numbers, interleaver block sizes and code rates.

• Proceedings of the IEEK Conference
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• 2003.11a
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• pp.83-86
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• 2003

In this paper, we propose a new hardware architecture for integer transform, quantizer operation of a new video coding standard H.264/JVT. We describe the algorithm to derive hardware architecture emphasizing the importance of area for low cost and low power consumption. The proposed architecture has been verified by PCI-interfaced emulation board using APEX-II Altera FPGA and also by ASIC synthesis using Samsung 0.18 ${\mu}{\textrm}{m}$ CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 100 MHz, processing more than 1, 300 QCIF video frames per second. The hardware is going to be used as a core module when implementing a complete H.264 video encoder/decoder ASIC for real-time multimedia application.

• Korean Journal of Remote Sensing
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• v.39 no.6_3
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• pp.1771-1777
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• 2023

With the advancements of deep learning, many semantic segmentation-based methods for land cover classification have been proposed. However, existing deep learning-based models only use image information and cannot guarantee spatiotemporal consistency. In this study, we propose a land cover classification model using geographical coordinates. First, the coordinate features are extracted through the Coordinate Hash Encoder, which is an extension of the Multi-resolution Hash Encoder, an implicit neural representation technique, to the longitude-latitude coordinate system. Next, we propose an architecture that combines the extracted coordinate features with different levels of U-net decoder. Experimental results show that the proposed method improves the mean intersection over union by about 32% and improves the spatiotemporal consistency.

• Journal of Information Processing Systems
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• v.1 no.1 s.1
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• pp.27-31
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• 2005

Vehicle detector system based on image processing technology is a significant domain of ITS (Intelligent Transportation System) applications due to its advantages such as low installation cost and it does not obstruct traffic during the installation of vehicle detection systems on the road[1]. In this paper, we propose architecture for vehicle detection by using image processing. The architecture consists of two main parts such as an image processing part, using high speed FPGA, decision and calculation part using CPU. The CPU part takes care of total system control and synthetic decision of vehicle detection. The FPGA part assumes charge of input and output image using video encoder and decoder, image classification and image memory control.

• Journal of Auto-vehicle Safety Association
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• v.16 no.1
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• pp.29-34
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• 2024

This paper presents a multi-label lane detection method for autonomous vehicles based on deep learning. The proposed algorithm can detect two types of lanes: center lane and normal lane. The algorithm uses a convolution neural network with an encoder-decoder architecture to extract features from input images and produce a multi-label heatmap for predicting lane's label. This architecture has the potential to detect more diverse types of lanes in that it can add the number of labels by extending the heatmap's dimension. The proposed algorithm was tested on an OpenLane dataset and achieved 85 Frames Per Second (FPS) in end to-end inference time. The results demonstrate the usability and computational efficiency of the proposed algorithm for the lane detection in autonomous vehicles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.335-342
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• 2016

This paper proposes efficient hardware structure of in-loop filter for a high-performance HEVC (High Efficiency Video Coding) encoder. HEVC uses in-loop filter consisting of deblocking filter and SAO (Sample Adaptive Offset) to improve the picture quality in a reconstructed image due to a quantization error. However, in-loop filter causes an increase in complexity due to the additional encoder and decoder operations. A proposed in-loop filter is implemented as a three-stage pipeline to perform the deblocking filtering and SAO operation with a reduced number of cycles. The proposed deblocking filter is also implemented as a six-stage pipeline to improve efficiency and performs a new filtering order for efficient memory architecture. The proposed SAO processes six pixels parallelly at a time to reduce execution cycles. The proposed in-loop filter encoder architecture is designed by Verilog HDL, and implemented by 131K logic gates in TSMC $0.13{\mu}m$ process. At 164MHz, the proposed in-loop filter encoder can support 4K Ultra HD video encoding at 60fps in real time.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1940-1943
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• 2002

In this paper, we presented the design and implementation of 155Mbps satellite Modem adaptively compensated against the rain attenuation. In order to compensate the rain attenuation over high-speed satellite ink, the adaptive coding schemes with variable coding rates and the pragmatic TCM that can be decoded both the QPSK and TC-8PSK using same Viterbi decoder was studied and analyzed. The pragmatic TCM with rate 213, selected to the optimal parameters for implementation, was modeled by VHDL in this paper. The key design issues are how to achieve a high data rate and how to integrated into a single ASIC chip various functions such as the different data rates, Scrambler/descrambler, Interleaver, Encoder/decoder, and BPSK/QPSK/8PSK modulator/demodulator. The implemented 155M0ps adaptive MODEM has the simplified interface circuits among the many functional blocks, and parallel processing architecture to achieve the high data rate. This 155Mbps adaptive MODEM was designed and implemented by single ASIC chip with the 0.25 $\mu\textrm{m}$ CMOS standard cell technology.