• 한국전기전자재료학회논문지
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• 제35권6호
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• pp.616-621
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• 2022

Numerical simulation is a good way to predict the conversion efficiency of solar cells without a direct experimentation and to achieve low cost and high efficiency through optimizing each step of solar cell fabrication. TOPCon industrial solar cells fabricated with n-type silicon wafers on a larger area have achieved a higher efficiency than p-type TOPCon solar cells. Electrical and optical losses of the front surface are the main factors limiting the efficiency of the solar cell. In this work, an optimization of boron-doped emitter surface and front electrodes through numerical simulation using "Griddler" is reported. Through the analysis of the results of simulation, it was confirmed that the emitter sheet resistance of 150 Ω/sq along the front electrodes having a finger width of 20 ㎛, and the number of finger lines ~130 for silicon wafer of M6 size is an optimized technology for the front emitter surface of the n-type TOPCon solar cells that can be developed.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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• pp.789-791
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• 1998

Numerical simulation has been performed on a microtip field emitter structure produced by employing a CMP technology. The field distributions are estimated by using a Maxwell 2D vector simulator and the electron trajectories are obtained by solving the equation of ballistic motion of emitted electrons. The beam width observed at the phosphor has been characterized as a function of the applied voltages and the gate-to-tip distance. It has also been investigated how the electron trajectory is changed by adopting the anode switching as well as the focus electrode.

• Current Photovoltaic Research
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• 제9권4호
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• pp.123-127
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• 2021

This study was on electrode design for the realization of a solar cell that combines electrode formation and module integration process to overcome printing limitations. We used the passivated emitter rear contact (PERC) solar cell. Wafer size was 156.75 mm ×156.75 mm. The fabricated cell results showed that the open-circuit voltage of 649 mV, short-circuit current density of 36.15 mA/cm², fill factor of 68.5%, and efficiency of 16.06% with electrode conditions the 24BBs with the width 190 ㎛ and 90FBs with the width 45 ㎛. For improving efficiency, the characteristics of the solar cell were checked according to the change in the number of BBs and FBs and the change in line fine width. It is confirmed that the efficiency of the solar cell will be improved by increasing the number of FBs from 90 to 120, and increasing the line width of the FBs by about 10 ㎛ compared to the manufacturing solar cells.

• 전자공학회논문지A
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• 제30A권10호
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• pp.41-50
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• 1993

This paper describes the fabrication process and electrical characteristics of PSA (Polysilicon Self-Align) bipolar transistors with a thin base width of 1100.angs.. To realize this shallow junction depth, one-step rapid thermal annealing(RTA) technology has been applied instead of conventional furnace annealing process. It has been shown that the series resistances and parasitic capacitances are significantly reduced in the device with emitter area of 1${\times}4{\mu}m^{2}$. The switching speed of 2.4ns/gate was obtained by measuring the minimum propagation delay time in the I$^{2}$L ring oscillator with 31 stages.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 1999년도 춘계종합학술대회
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• pp.415-419
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• 1999

Many bipolar logic circuit of conventional occurred problem of speed delay according to deep saturation state of vertical NPN Transistor. In order to remove minority carries of the base region at changing signal in conventional bipolar logic circuit, we made transistor which is composed of NPN transistor shortened buried layer under the Base region, PNP transistor which is merged in base, epi layer and substrate. Also the Ring-Oscillator for measuring transmission time-delay per gate was designed as well. The structure of Gate consists of the vertical NPN Transistor, substrate and Merged PNP Transistor. In the result, we fount that tarriers which are coming into intrinsic Base from Emitter and the portion of edge are relatively a lot, so those make Base currents a lot and Gain is low with a few of collector currents because of cutting the buried layer of collector of conventional junction area. Merged PNP Transistor's currents are low because Base width is wide and the difference of Emitter's density and Base's density is small. we get amplitude of logic voltage of 200mv, the minimum of transmission delay-time of 211nS, and the minimum of transmission delay-time per gate of 7.26nS in AC characteristic output of Ring-Oscillator connected Gate.

• International Journal of Aeronautical and Space Sciences
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• 제12권2호
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• pp.175-178
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• 2011

An optical fiber-based beam width measurement technique is presented. The proposed system can be applied to the optical fiber industry in applications such as lensed fiber, optical fiber based laser beam source, and fiber optic sensor. The measurement system is composed of optical fiber, which is used as a transceiver, and a single grating panel which consists of a multi-reflection area with an even non-reflection area. The grating panel is used to vary the reflected light. When the widths of the reflection area and non-reflection area are larger than the optical beam width, the reflected light is varied at the interface between the reflection area and the non-reflection area by the movement of the grating panel. Experiments were conducted in order to verify the feasibility of the proposed technique. Multi-mode fiber combined with a collimator was selected as an emitter and a receiver, and the beam width measurement system was contrived. Subsequently, the proposed method and the system were verified by comparing the experimental results with the results of the conventional charge-coupled device technique.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.927-930
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• 2004

We report on a new type of a flat and thin display with a secondary emission electron source. In this display device electrons are multiplied between two secondary emission plates under a high frequency electric field. This principle has a few important advantages over a field emission display: the emission comes from flat plates, which reduces the life-time problems of ion bombardment of field emitter tips. Furthermore, the electron emission is space charge limited which gives a uniform electron distribution. The electrons are extracted from the source and accelerated to a phosphor screen to generate light. Gray levels are made by pulse width modulation.

• 전자공학회논문지B
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• 제33B권3호
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• pp.56-61
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• 1996

In this paper, new buck converter of a TV power system is presented. First, we devised a revised driving circuit for an emitter-coupled type buck converter, by which it is possible to reduce the material cost of transformers and voltage stress of power device. Secondly, we adopted a hybrid oscillation technique. When TV system is in off-stage, initial standby power which is necessary for remote controllable TV system is supplied by self-oscillating mode. Main power which is necessry in TV system bing on state is provided by an externally triggered oscillating mode. The switching frequency is synchronized to the oscillating frequency of horizontal deflection in TV, by which we can reduce picture noises and the size of power transformer. Thirdly, a simple error amplifier is inserted to the feed-back loop to keep the output voltage constant which means pulse width modulatio mode is added in driving part of power device. Finally, we showed by experiments that our proposed converter performs well enough to be close to the theoretically predicted values.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 하계학술대회 논문집
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• pp.243-246
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• 2001

Thyristor devices have 3-dimensional complicated structure and were sensitive to temperature characteristics. Therefore, it was difficult to optimize thyristor devices design. We have to consider many design parameter to characterize, and trade-off relations. The important parameters to design thyristor devices are cathode structure, effective line width, cathode-emitter shunt structure, gate structure, doping profile and carrier lifetime. So, we must consider that these design parameters were not acted separately. However, there are many difficulties to determine optimized design parameters by experiment. So, We used specific design software to design thyristor devices, and estimated the thyristor devices characteristics.

• 대한전자공학회논문지SD
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• 제38권2호
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• pp.28-28
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• 2001

능동제어형 전계방출 디스플레이의 전자공급원으로서 능동제어형 전계 에미터 어레이의 회로모델이 제안되었다. 능동제어형 전계 에미터 어레이는 전계방출을 안정화시키고 저전력구동을 위한 수소화 된 비정질 실리콘 박막 트랜지스터와 Spindt형 Mo 전계 에미터 어레이로 구성되었고 같은 유리기판 위에 제작되었다. 비정질 박막 트랜지스터와 Spindt형 Mo 전계 에미터 어레이의 전기적 특성으로부터 추출된 기본 모델 변수는 제안된 능동제어형 전계 에미터 어레이 회로모델에 입력되었고 SPICE 회로 시뮬레이터를 사용하여 특성을 분석하였다. 제작된 소자의 측정값과 DC 시뮬레이션 결과를 비교한 결과 두 값이 상당히 일치함으로써 등가회로 모델의 정확성을 확인하였다. 또한 제작된 소자의 transient 시뮬레이션 결과 전계 에미터 어레이의 게이트 커패시턴스와 TFT의 구동능력이 반응시간에 가장 크게 영향을 끼치고 있음을 확인하였다. 제작된 능동제어형 전계방출 에미터 어레이는 pulse width modulation으로 구동하는 경우 15㎲의 반응시간을 얻었고 이 값으로는 4bit/color의 계조(gray scale)표현이 가능하였다.