• 제목/요약/키워드: Emitter series resistance

검색결과 18건 처리시간 0.025초

ITO 에미터 투명전극을 갖는 InGaAs/InP HPT의 연구 (InGaAs/InP HPT's with ITO Transparent Emitter Contacts)

  • 한교용
    • 한국전기전자재료학회논문지
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    • 제20권3호
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    • pp.268-272
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    • 2007
  • A fully integrable InP/InGaAs HPT with an ITO emitter contact was first fabricated by employing a $SiO_2$ passivation layer. The electrical and the optical characteristics of the HPT with a passivation layer were measured and compared with those of the HPT without a passivation layer. The only noticeable difference was the increased emitter series resistance of the HPT with a passivation layer. AES analysis was performed to explain the reason of the increased emitter series resistance. Results show that PECVD $SiO_2$ deposition and annealing processes cause the diffusion of oxygen to the interface and the depletion of tin at the interface, which may be responsible for the increase of the series resistance.

고면저항 에미터 결정질 실리콘 태양전지의 전면전극 접촉저항 분석 (Contact Resistance Analysis of High-Sheet-Resistance-Emitter Silicon Solar Cells)

  • 안준용;정주화;도영구;김민서;정지원
    • 신재생에너지
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    • 제4권2호
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    • pp.74-80
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    • 2008
  • To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

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고면저항 에미터 결정질 실리콘 태양전지의 전면전극 접촉저항 분석 (CONTACT RESISTANCE ANALYSIS OF HIGH-SHEET-RESISTANCE-EMITTER SILICON SOLAR CELLS)

  • 안준용;정주화;도영구;김민서;정지원
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2008년도 춘계학술대회 논문집
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    • pp.390-393
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    • 2008
  • To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

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결정질 실리콘 태양전지의 고효율 화를 위한 Selective emitter 구조 및 Ni/Cu plating 전극 구조 적용에 관한 연구 (PA study on selective emitter structure and Ni/Cu plating metallization for high efficiency crystalline silicon solar cells)

  • 김민정;이재두;이수홍
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2010년도 춘계학술대회 초록집
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    • pp.91.2-91.2
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    • 2010
  • The use of plated front contact for metallization of silicon solar cell may alternative technologies as a screen printed and silver paste contact. This technologies should allow the formation of contact with low contact resistivity a high line conductivity and also reduction of shading losses. The better performance of Ni/Cu contacts is attributed to the reduced series resistance due to better contact conductivity of Ni with Si and subsequent electroplating of Cu on Ni. The ability to pattern narrower grid lines for reduced light shading combined with the lower resistance of a metal silicide contact and improved conductivity of plated deposit. This improves the FF as the series resistance is deduced. This is very much required in the case of low concentrator solar cells in which the series resistance is one of the important and dominant parameter that affect the cell performance. A selective emitter structure with highly dopes regions underneath the metal contacts, is widely known to be one of the most promising high-efficiency solution in solar cell processing. This paper using selective emitter structure technique, fabricated Ni/Cu plating metallization cell with a cell efficiency of 17.19%.

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Selective Emitter 구조를 적용한 Ni/Cu Plating 전극 결정질 실리콘 태양전지 (Application of a Selective Emitter Structure for Ni/Cu Plating Metallization Crystalline Silicon Solar Cells)

  • 김민정;이재두;이수홍
    • 한국전기전자재료학회논문지
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    • 제23권7호
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    • pp.575-579
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    • 2010
  • The technologies of Ni/Cu plating contact is attributed to the reduced series resistance caused by a better contact conductivity of Ni with Si and the subsequent electroplating of Cu on Ni. The ability to pattern narrower grid lines for reduced light shading was combined with the lower resistance of a metal silicide contact and an improved conductivity of the plated deposit. This improves the FF (fill factor) as the series resistance is reduced. This is very much requried in the case of low concentrator solar cells in which the series resistance is one of the important and dominant parameter that affect the cell performance. A Selective emitter structure with highly dopeds regions underneath the metal contacts, is widely known to be one of the most promising high-efficiency solution in solar cell processing In this paper the formation of a selective emitter, and the nickel silicide seed layer at the front side metallization of silicon cells is considered. After generating the nickel seed layer the contacts were thickened by Cu LIP (light induced plating) and by the formation of a plated Ni/Cu two step metallization on front contacts. In fabricating a Ni/Cu plating metallization cell with a selective emitter structure it has been shown that the cell efficiency can be increased by at least 0.2%.

ITO 투명전극을 갖는 InP/InGaAs HPTs 제작 (Fabrication of InP/InGaAs HPT with ITO Transparent Emitter Contact)

  • 김용근;장은숙;최병건;신주선;성광수;한교용
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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    • pp.229-232
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    • 2000
  • InP/lnGaAs HPT's were fabricated by employing Indium Tin Oxide(ITO) transparent emitter contact. The device showed the current gaing 70 was obtained but the emitter series resistance was significantly increased. the electrical charateristics of the device were similar to HBT's. However Vceoff was shifted the positive direction. Such a shift ma be resulted from the formation of the shottky barrier rather than the ohmic contact between ITO and n+ InP emitter.

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열산화법에 의한 phosphorus 에미터 pile-up (Pile-up of phosphorus emitters using thermal oxidation)

  • 부현필;강민구;이경동;이종한;탁성주;김영도;박성은;김동환
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2011년도 춘계학술대회 초록집
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    • pp.122.1-122.1
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    • 2011
  • Phosphorus is known to pile-up at the silicon surface when it is thermally oxidized. A thin layer, about 40nm thick from the silicon surface, is created containing more phosphorus than the bulk of the emitter. This layer has a gaussian profile with the peak at the surface of the silicon. In this study the pile-up effect was studied if this layer can act as a front surface field for solar cells. The effect was also tested if its high dose of phosphorus at the silicon surface can lower the contact resistance with the front metal contact. P-type wafers were first doped with phosphorus to create an n-type emitter. The doping was done using either a furnace or ion implantation. The wafers were then oxidized using dry thermal oxidation. The effect of the pile-up as a front surface field was checked by measuring the minority carrier lifetime using a QSSPC. The contact resistance of the wafers were also measured to see if the pile-up effect can lower the series resistance.

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TCO/Si 접합 EWT 태양전지에 관한 전기적 및 광학적 특성 (Electrical and Optical Properties for TCO/Si Junction of EWT Solar Cells)

  • 송진섭;양정엽;이준석;홍진표;조영현
    • 한국신재생에너지학회:학술대회논문집
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    • 한국신재생에너지학회 2010년도 추계학술대회 초록집
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    • pp.39.2-39.2
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    • 2010
  • In this work we have investigated electrical and optical properties of interface for ITO/Si with shallow doped emitter. The ITO is prepared by DC magnetron sputter on p-type monocrystalline silicon substrate. As an experimental result, The transmittance at 640nm spectra is obtained an average transmittance over 85% in the visible range of the optical spectrum. The energy bandgap of ITO at oxygen flow from 0% to 4% obtained between 3.57eV and 3.68eV (ITO : 3.75eV). The energy bandgap of ITO is depending on the thickness, sturcture and doping concentration. Because the bandgap and position of absorption edge for degenerated semiconductor oxide are determined by two competing mechanism; i) bandgap narrowing due to electron-electron and electron-impurity effects on the valance and conduction bands (> 3.38eV), ii) bandgap widening by the Burstein-Moss effect, a blocking of the lowest states of the conduction band by excess electrons( < 4.15eV). The resistivity of ITO layer obtained about $6{\times}10^{-4}{\Omega}cm$ at 4% of oxygen flow. In case of decrease resistivity of ITO, the carrier concentration and carrier mobility of ITO film will be increased. The contact resistance of ITO/Si with shallow doped emitter was measured by the transmission line method(TLM). As an experimental result, the contact resistance was obtained $0.0705{\Omega}cm^2$ at 2% oxygen flow. It is formed ohmic-contact of interface ITO/Si substrate. The emitter series resistance of ITO/Si with shallow doped emitter was obtained $0.1821{\Omega}cm^2$. Therefore, As an PC1D simulation result, the fill factor of EWT solar cell obtained above 80%. The details will be presented in conference.

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직렬 궤환을 이용한 아날로그 전치왜곡 선형화기 (An Analog Predistortion Linearizer using Series Feedback Structure)

  • 김일규;전기경;김영;윤영철
    • 한국항행학회논문지
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    • 제10권3호
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    • pp.256-262
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    • 2006
  • 본 논문에서는 증폭기의 비선형 특성인 AM/AM 과 AM/PM 현상을 보상해주는 새로운 형태의 선형화기를 제안하였다. 이 선형화기는 공통 이미터 증폭기와 쇼트키 다이오드를 이미터와 접지 사이에 연결한 형태로 구성되어 있어, 쇼트키 다이오드의 접합 저항 값이 변화함에 따라 이득 증가 와 위상 확장 특성을 얻을 수 있다. 이러한 결과를 이용하여 증폭기의 비선형 특성을 개선시킬 수 있으며, 셀룰라 기지국 주파수 밴드의 증폭기를 제작하여 증폭기의 비선형 특성 개선을 확인하였다. 반송파 2톤 신호를 인가하였을 때, 주파수 간격이 1MHz에서 3차 혼변조 신호는 10.4dB 개선되었고, IS-95 CDMA 1FA 신호에서는 인접채널 전력비가 9.6dB 개선됨을 확인하였다.

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실리콘 태양전지 최적설계에 관한 연구 (A Study on Optimal Design of Silicon Solar Cell)

  • 유진수;문상일;김경해;;이준신
    • 대한전기학회논문지:전기물성ㆍ응용부문C
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    • 제53권4호
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    • pp.187-191
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    • 2004
  • In this work, we used the PCID simulator for simulation of solar cell and examined the effect of front-back surface recombination velocity, minority carrier diffusion length, junction depth and emitter sheet-resistance. As the effect of base thickness, the efficiency decreased by the increase in series resistance with the increase of the thickness and found decrease in efficiency by decrease of the current as the effect of the recombination. Also, as the effect of base resistivity, the efficiency increased somewhat with the decrease in resistivity, but when the resistivity exceeded certain value, the efficiency decreased as a increase in the recombination ratio. The optimum efficiency was obtained at the resistivity 0.5 $\Omega$-cm, and thickness $100\mu\textrm{m}$. We have successfully achieved 10.8% and 13.7% efficiency large area($103mm{\times}103mm$) mono-crystalline silicon solar cells without and with PECVD silicon nitride antireflection coating.