• 신재생에너지
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• 제4권2호
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• pp.74-80
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• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2008년도 춘계학술대회 논문집
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• pp.390-393
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• 2008

To improve the blue responses of screen-printed single crystalline silicon solar cells, we investigated an emitter etch-back technique to obtain high emitter sheet resistances, where the defective dead layer on the emitter surface was etched and became thinner as the etch-back time increased, resulting in the monotonous increase of short circuit current and open circuit voltage. We found that an optimal etch-back time should be determined to achieve the maximal performance enhancement because of fill factor decrease due to a series resistance increment mainly affected by contact and lateral resistance in this case. To elucidate the reason for the fill factor decrease, we studied the resistance analysis by potential mapping to determine the contact and the lateral series resistance. As a result, we found that the fill factor decrease was attributed to the relatively fast increase of contact resistance due to the dead layer thinning down with the lowest contact resistivity when the emitter was contacted with screen-printed silver electrode.

• Current Photovoltaic Research
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• 제4권2호
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• pp.54-58
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• 2016

Laser-doped selective emitter process requires dopant source deposition, spin-on-glass, and is able to form selective emitter through SiNx layer by laser irradiation on desired locations. However, after laser doping process, the remaining dopant layer needs to be washed out. Laser-induced melting of pre-deposited impurity doping is a precise selective doping method minimizing addition of process steps. In this study, we introduce a novel scheme for fabricating highly efficient selective emitter solar cell by laser doping. During this process, laser induced damage induces front contact destabilization due to the hindrance of silver nucleation even though laser doping has a potential of commercialization with simple process concept. When the laser induced damage is effectively removed using solution etch back process, the disadvantage of laser doping was effectively removed. The devices fabricated using laser doping scheme power conversion efficiency was significantly improved about 1% abs. after removal the laser damages.

• 한국진공학회지
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• 제6권2호
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• pp.103-108
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• 1997

본 연구에서는 2단계 실리콘 건식식각 공정과 게이트 절연막으로 열산화막과 tetraethylorthosilicate(TEOS) 산화막의 이중막을 사용하고, 스핀-온-그래스 (Spin-on-glass:SOG) 에치백(etch-back) 공정에 의하여 게이트를 제작하는 새로운 방법을 통하여 실리콘 전계방출소자를 제작하고 그 특성을 분석하였다. 게이트 절연막의 누설전류 를 감소시키면서 팁과 게이트의 간격을 줄이는 구조인 이중 게이트 절연막을 형성하기 위하 여 팁 첨예화 산화 공정후 낮은 점도의 감광막(photo resist)을 시료에 도포한 후, $O_2$ 플라 즈마 에싱(ashing)하는 공정을 채택하였다. 이러한 공정으로 제작된 에미터 팁의 높이와 팁 반경은 각각 1.1$\mu\textrm{m}$와 100$\AA$정도이었으며, 256개 팁 어레이에서 전계방출의 문턱전압은 40V 이하이었다. 60V의 게이트전압에서 23$\mu\textrm{A}$(즉, 90nA/팁)의 높은 아노드 전류를 얻을 수 있었 다. 이때, 게이트 전류는 아노드전류의 약0.1%이하였다. 개발된 공정기술로 게이트 개구도 크게 감소시켰을 뿐 아니라, 게이트 누설전류를 현저히 감소시켰다.

• 한국신재생에너지학회:학술대회논문집
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• 한국신재생에너지학회 2009년도 추계학술대회 논문집
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• pp.347-347
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• 2009

결정질 태양전지의 공정에 있어서 호모지니어스(homogeneous)한 구조보다 향상된 변환효율을 얻기 위해 선택적 도핑 방법에 관한 연구가 활발하다. 선택적 도핑 방법이란 에미터(emitter) 층을 $n^{++}$ 영역과 $n^+$ 영역으로 나누어 향상된 전류밀도와 개방전압을 얻기 위한 방법이다. 본 연구에서 제시된 RIE 에치-백 구조는 다수의 선택적 도핑 방법 중 하나이다. 기존의 에치-백 구조는 전면 전극 형성 후 RIE 공정을 수행하기 때문에 전면 전극이 손상되고 RIE 데미지(damage)가 발생되는 문제점이 있었다. 그러나 본 연구에서 제시된 구조는 기존의 에치-백 구조와 달리 RIE 에칭 후 발생된 데미지를 제거하는 추가적인 공정인 질산 패시베이션(nitric acid passivation)이 수행되었다. 또한 본 연구에서 새롭게 제시된 블라킹 마스크 페이스트(blocking mask paste)는 기존의 에치-백 구조에서 발생된 전극 손상 문제를 해결해 주고 있다. 이러한 결과로 호모지니어스 구조보다 향상된 전류밀도 (35.77 mA/$cm^2$), 개방전압 (625 mV), FF (78.01%), 변환효율 (17.43%)를 얻었다.

• 한국태양에너지학회:학술대회논문집
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• 한국태양에너지학회 2011년도 추계학술발표대회 논문집
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• pp.40-44
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• 2011

Recent studies in crystalline silicon solar cell fabrication have been focused on high efficiency and low cost. However, the rising of the cost results in additional processes to approach high efficiency. The fabrication process also becomes complicated with additional technologies. In this paper, we studied the selective emitter formation with phosphorous paste to improve the conversion efficiency. Selective emitter formations like two-step diffusion or etch-back method require at least one more step compared in the conventional line since heavily and lightly doped area was needed to form separately.However,one-step diffusion process is the method diffusing heavily and lightly doped area at the same time only with additional screen-printing step. This study lays the foundation for the simple way to form the selective emitter.

• Current Photovoltaic Research
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• 제2권3호
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• pp.130-134
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• 2014

We have fabricated the selective emitter solar cell using double textured nanowires structure. The $40{\times}40mm2$-sized silicon substrates were textured to form the pyramid-shaped surface and the nanowires were fabricated by metal assisted chemical etching process using Ag nanoparticles, subsequently. The heavily doped and shallow emitters for selectiv eemitter solar cells were prepared through the thermal $POCl_3$ diffusion and chemical etch-back process, respectively. The front and rear electrodes were prepared following conventional screen printing method and the widths of fingers have been optimized. The selective emitter solar cell using double textured nanowires structure achieved a conversion efficiency of 17.9% with improved absorption and short circuit current density.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권7호
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• pp.521-524
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• 1999

Nb silicide was formed on the Si micro-tip arrays in order to improve field emission properties of Si-tip field emitter array. After silicidization of the tips, the etch-back process, by which gate insulator, gate electrode and photoresist were deposited sequentially and gate holes were defined by removing gradually the photoresist by $O_2$ plasma from the surface, was applied. Si nitride film was used as a protective layer in order to prevent oxygen from diffusion into Nb silicide layer and it was identified that the NbSi2 was formed through annealing in $N_2$ ambient at $1100^{\circ}C$ for 1 hour. By the Nb silicide coating on Si tips, the turn-on voltage was decreased from 52.1 V to 32.3 V and average current fluctuation for 1 hour was also reduced from 5% to 2%. Also, the fabricated Nb silicide-coated Si tip FEA emitted electrons toward the phosphor and light emission was obtained at the gate voltage of 40~50 V.

• ETRI Journal
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• 제24권4호
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• pp.290-298
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• 2002

We present, for the first time, a prototype active-matrix field emission display (AMFED) in which an amorphous silicon thin-film transistor (a-Si TFT) and a molybdenum-tip field emitter array (Mo-tip FEA) were monolithically integrated on a glass substrate for a novel active-matrix cathode (AMC) plate. The fabricated AMFED showed good display images with a low-voltage scan and data signals irrespective of a high voltage for field emissions. We introduced a light shield layer of metal into our AMC to reduce the photo leakage and back channel currents of the a-Si TFT. We designed the light shield to act as a focusing grid to focus emitted electron beams from the AMC onto the corresponding anode pixel. The thin film depositions in the a-Si TFTs were performed at a high temperature of above 360°C to guarantee the vacuum packaging of the AMC and anode plates. We also developed a novel wet etching process for $n^+-doped$ a-Si etching with high etch selectivity to intrinsic a-Si and used it in the fabrication of an inverted stagger TFT with a very thin active layer. The developed a-Si TFTs performed well enough to be used as control devices for AMCs. The gate bias of the a-Si TFTs well controlled the field emission currents of the AMC plates. The AMFED with these AMC plates showed low-voltage matrix addressing, good stability and reliability of field emission, and good light emissions from the anode plate with phosphors.

• 한국재료학회지
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• 제10권4호
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• pp.301-304
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• 2000

Si FEA로 부터 tip의 표면을 Co 금속으로 silicidation한 새로운 3극형 Co-silicided Si FEA를 제작하고 이의 전계 방출특성을 조사하였다. $10^{-8}Torr$의 고진공상태에서 제작된 소자의 단위 pixel(pixel 면적 : $250{\mu\textrm{m}}{\times}250{\mu\textrm{m}}$, tip 어레이 : $45{\times}45$)를 통해 측정된 turn-on 전압은 약 35V로, 아노드 전류는 $V_A=500V,\;V_G=55V$ 바이어스 아래에서 약 $1.2{\mu\textrm{A}}(0.6nA/tip)$로 나타났다. 제작된 소자는 초기 과도상태를 제외하면 장시간의 동작을 통해 전계방출 전류의 감소없이 매우 안정된 전기적 특성을 나타내었다. Co-silicided Si FFA 의 낮은 turn-on 전압과 높은 전류안전성은 Si tip 표면에 형성된 실리사이드 박막의 열화학적 안전성과 낮은 일함수에 기인하는 것으로 판단된다.