• Journal of Institute of Control, Robotics and Systems
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• v.22 no.10
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• pp.797-802
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• 2016

This paper proposes a noble voice recognition method based on an adaptive MFCC and deep learning for embedded systems. To enhance the recognition ratio of the proposed voice recognizer, ambient noise mixed into the voice signal has to be eliminated. However, noise filtering processes, which may damage voice data, diminishes the recognition ratio. In this paper, a filter has been designed for the frequency range within a voice signal, and imposed weights are used to reduce data deterioration. In addition, a deep learning algorithm, which does not require a database in the recognition algorithm, has been adapted for embedded systems, which inherently require small amounts of memory. The experimental results suggest that the proposed deep learning algorithm and HMM voice recognizer, utilizing the proposed adaptive MFCC algorithm, perform better than conventional MFCC algorithms in its recognition ratio within a noisy environment.

• Proceedings of the IEEK Conference
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• summer
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• pp.204-208
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• 2004

Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.295-301
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• 2011

A triple-band transceiver module for 2.3/2.5/3.5 GHz mobile WiMAX, IEEE 802.16e, applications is introduced. The suggested transceiver module consists of RFIC, reconfigurable/multi-resonance MIMO antenna, embedded PCB, mobile WiMAX base band, memory and channel selection front-end module. The RFIC is fabricated in $0.13{\mu}m$ RF CMOS process and has 3.5 dB noise figure(NF) of receiver and 1 dBm maximum power of transmitter with 68-pin QFN package, $8{\times}8\;mm^2$ area. The area reduction of transceiver module is achieved by using embedded PCB which decreases area by 9% of the area of transceiver module with normal PCB. The developed triple-band mobile WiMAX transceiver module is tested by performing radio conformance test(RCT) and measuring carrier to interference plus noise ratio (CINR) and received signal strength indication (RSSI) in each 2.3/2.5/3.5 GHz frequency.

• Journal of Information Processing Systems
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• v.20 no.1
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• pp.116-130
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• 2024

In the Internet-of-Things (IoT) or blockchain-based network systems, secure keys may be stored in individual devices; thus, individual devices should protect data by performing secure operations on the data transmitted and received over networks. Typically, secure functions, such as a physical unclonable function (PUF) and fully homomorphic encryption (FHE), are useful for generating safe keys and distributing data in a network. However, to provide these functions in embedded devices for IoT or blockchain systems, proper inspection is required for designing and implementing embedded system-on-chip (SoC) modules through overhead and performance analysis. In this paper, a virtual platform (SoC VP) was developed that includes a secure key generation module with a PUF and FHE. The SoC VP platform was implemented using SystemC, which enables the execution and verification of various aspects of the secure key generation module at the electronic system level and analyzes the system-level execution time, memory footprint, and performance, such as randomness and uniqueness. We experimentally verified the secure key generation module, and estimated the execution of the PUF key and FHE encryption based on the unit time of each module.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.5
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• pp.33-37
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• 2013

In this paper, we introduce a SDRAM controller implemented on FPGA. Modern embedded system adopts SDRAM as a memory to meet the high capacity memory demands. Our SDRAM controller is written in Verilog and verified on an FPGA, demonstrating the functionality along with ARM Cortex-M0, supporting AMBA AHB.

• Proceedings of the Korean Society For Composite Materials Conference
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• 2001.05a
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• pp.151-154
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• 2001

Shape memory alloy (SMA) has demonstrated its potentials for various smart structure applications. SMA wires undergo a reversible phase transformation from martensite to austenite as temperature increases. This transformation leads to shape recovery and associated recovery strains. If SMA actuators are embedded off the neutral surface and are oriented in arbitrary angles with respect to a beam axis, then the beam bends and twists due to the coupling effects of recovery strains activated. In this study, the bending and twisting of a SMA/Composite beam were controlled by both electric resistive heating and passive elastic tailoring. 3-dimensional finite element formulations were derived and validated to analyze the responses of the SMA/Composite beam. Numerical results show that the shape of the SMA/Composite beam can be controlled by judicious choices of control temperatures, SMA angles, and elastic tailoring.

• International Journal of Aeronautical and Space Sciences
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• v.8 no.2
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• pp.76-81
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• 2007

The fiber reinforced laminated composite structures are very susceptible to be damaged when they are impacted by foreign objects. To increase the impact resistance of the laminated composite structures, shape memory alloy(SMA) thin film is embedded in the structure. For the numerical impact analysis of SMA hybrid composite structures, SMA modeling tool is developed to consider pseudoelastic effect of SMAs. Moreover, the damage analysis is considered using failure criteria and a simple damage model for reasonable impact analysis. The numerical results are verified with the experimental ones. Impact analyses for composite plate with pre-strained SMAs are numerically performed and the damage areas are investigated.

• Research in Mathematical Education
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• v.17 no.3
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• pp.199-220
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• 2013

The main objective of this study is to explore the relationship between psychological factors (i.e. math anxiety, attention, attitude, Working Memory Capacity (WMC), and Field dependency) and students' mathematics problem solving based on Revised Bloom Taxonomy. A sample of 169 K11 school girls were tested on (1) The Witkin's cognitive style (Group Embedded Figure Test). (2) Digit Span Backwards Test. (3) Mathematics Anxiety Rating Scale (MARS). (4) Modified Fennema-Sherman Attitude Scales. (5) Mathematics Attention Test (MAT), and (6) Mathematics questions based on Revised Bloom Taxonomy (RBT). Results obtained indicate that the effect of these items on students mathematical problem solving is different in each cognitive process and level of knowledge dimension.

• Proceedings of the Korean Information Science Society Conference
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• 2006.06a
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• pp.346-348
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• 2006

실시간 운영체제를 탑재한 임베디드 시스템(Embedded System)은 특성상 다른 시스템에 비해 상대적으로 저 용량의 메모리를 지닌다. 따라서 제한된 메모리를 효율적으로 사용할 수 있는 기법이 적용될 필요가 있다. 외부 단편화(External Fragmentation)로 생긴 메모리 공간을 재조정하는 기법도 효율적인 메모리 사용을 위한 방안이며, 본 논문에서는 실시간 운영체제에서 가용한 메모리를 효율적으로 활용할 수 있는 메모리 압축(Memory Compaction) 기법에 대해서 설계 및 구현하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.260-260
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• 2010

현대 사회가 고도의 정보화 사회로 변화하는 가운데 능동행렬 액정 표시 소자(AMLCD : Active Matrix Liquid Crystal Display)는 정보 디스플레이 분야에서 없어서는 안될 중요한 위치를 차지하게 됐다. AMOLED는 자체발광형이므로 LCD에 비해 시야각, contrast, 시인성이 우수하며, 화소를 낮은 전류 밀도로 구동시킨다는 장점이 있다. OLED 소자는 각 화소를 구동할 수 있는 박막 트랜지스타가 필요하며, OLED 소자와 결합된 TFT의 연구도 진행되고 있다. 더욱이 모바일 소자에서 낮은 구동 전압과 비용의 절감을 위해 System On Panels (SOP)에 대한 연구가 또한 진행되고 있다. LCD 패널위에 콘트롤러와 메모리와 같은 소자를 직접화시킴으로써 액정 표시 장치를 소형화시킬 수 있으며 신뢰성을 향상시킬 수가 있다. 본 연구에서는 SOP를 위한 ELA 방법을 통하여 결정화한 poly-Si TFT memory를 제작하여 전기적 특성을 조사하였다.