• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.571-574
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• 2008

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• 정보저장시스템학회:학술대회논문집
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• 2005.10a
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• pp.96-102
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• 2005

The tribocharge build-up in the slider disk interface can cause ESD (electrostatic discharge) damage. In turn, ESD can cause severe melting damage to MR or GMR heads. We investigated the tribovoltage/current build-up with smooth and textured disks in HDD, operating at increasing disk accelerations. We found that tribe-voltage/current were generated during pico-slider/disk interaction and those levels were about 0.1 ${\~}$ 0.3 V and 10 ${\~}$ 40 pA, respectively. Tribovoltage/current were abruptly increased and dissipated within the acceleration time in the case of textured disk but in the case of smooth disk tribovoltage was continuously increased until the end of uniform velocity region and the tribocurrent did not dissipate within the acceleration time. In the case of textured dist tribovoltage/current was reduced with increasing disk acceleration, but in the case of smooth disk it was increased.

• Proceedings of the IEEK Conference
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• summer
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• pp.82-85
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• 2004

This paper proposes an advanced circuit for the capacitive type fingerprint sensor signal processing and an effective isolation structure for minimizing an electrostatic discharge(ESD) influence and for removing a signal coupling noise of each sensor pixel. The proposed detection circuit increases the voltage difference between a ridge and valley about $80\%$ more than old circuit. The test chip is composed of $160\;\times\;192$ array sensing cells $(9,913\times11,666\;um^2).$ The sensor plate area is $58\;\times\;58\;um^2$ and the pitch is 60um. The image resolution is 423 dpi. The chip was fabricated on a 0.35um standard CMOS process. It successfully captured a high-quality fingerprint image and performed the registration and identification processing. The sensing and authentication time is 1 sec(.) with the average power consumption of 10 mW at 3.0V. The reveal ESD tolerance is obtained at the value of 4.5 kV.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.13 no.3
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• pp.531-536
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• 2009

In this paper, we propose $256{\times}256$ pixel array fingerprint sensor with an advanced circuits for detecting. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. We minimizes an electrostatic discharge(ESD) influence by applying an effective isolation structure around the unit pixel. The sensor circuit blocks were designed and simulated in standard CMOS $0.35{\mu}m$ process. Full custom layout is performed in the unit sensor pixel and auto placement and routing is performed in the full chip.

• Korean Journal of Materials Research
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• v.29 no.2
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• pp.106-115
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• 2019

Recently, metal cases are widely used in smart phones for their luxurious color and texture. However, when a metal case is used, electric shock may occur during charging. Chip capacitors of various values are used to prevent the electric shock. However, chip capacitors are vulnerable to electrostatic discharge(ESD) generated by the human body, which often causes insulation breakdown during use. This breakdown can be eliminated with a high-voltage chip varistor over 340V, but when the varistor voltage is high, the capacitance is limited to about 2pF. If a chip capacitor with a high dielectric constant and a chip varistor with a high voltage can be combined, it is possible to obtain a new device capable of coping with electric shock and ESD with various capacitive values. Usually, varistors and capacitors differ in composition, which causes different shrinkage during co-firing, and therefore camber, internal crack, delamination and separation may occur after sintering. In addition, varistor characteristics may not be realized due to the diffusion of unwanted elements into the varistor during firing. Various elements are added to control shrinkage. In addition, a buffer layer is inserted in the middle of the varistor-capacitor junction to prevent diffusion during firing, thereby developing a co-fired product with desirable characteristics.

• Transactions on Electrical and Electronic Materials
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• v.7 no.1
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• pp.1-6
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• 2006

Hot carrier degradation and roll off characteristics of threshold voltage ($V_{t1}$) on NMOSFETs as I/O transistor are studied as a function of Lightly Doped Drain (LDD) structures. Pocket dose and the combination of Phosphorus (P) and Arsenic (As) dose are applied to control $V_{t1}$ roll off down to the $10\%$ gate length margin. It was seen that the relationship between $V_{t1}$ roll off characteristic and substrate current depends on P dopant dose. For the first time, we found that the n-p-n transistor triggering voltage ($V_{t1}$) depends on drain current, and both $I_{t2}$ and snapback holding voltage ($V_{sp}$) depend on the substrate current by characterization with a transmission line pulse generator. Also it was found that the improved lifetime for hot carrier stress could be obtained by controlling the P dose as loosing the $V_{t1}$ roll off margin. This study suggests that the trade-off characteristic between gate length margin and channel hot carrier (CHC) lifetime in NMOSFETs should be determined by considering Electrostatic Discharge (ESD) characteristic.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.63 no.2
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• pp.319-324
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• 2014

The wafer carrier is made of PP, PC, PE resin which have excellent heat and chemical resistance and electrical properties. However, particle generation has become a problem due to static electricity generated in the carrier. Some conductive material such as carbon black (CB) and carbon fiber (CF) are added for the purpose of anti-static, however, additional for motility and particle contamination problems due to high carbon content occurs. In this paper, the electrical characteristics and workability are observed and compared by adding low Carbon Nono Tube(CNT) to each PP, PC and PE resin to solve the problem.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.391-392
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• 2008

A SPICE-based 3-dimensional circuit model of Light-Emitting Diode(LED) was modified include the reverse breakdown properties. The new model is found to be accurate to study the failure mechanisms of LEDs under electrostatic discharge (ESD) and electronic overstress (EOS). It was found that the permanent damages under heavy reverse stress is mainly due to the high electric field strength in P-GaN layer.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.5
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• pp.366-372
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• 2017

In this paper, the analysis of baluns that are inevitably required to design a differential low noise amplifier, The balun converts a single signal input from the antenna into a differential signal, which serves as an input to the differential amplifier. In addition, it protects the circuit from ESD(Electrostatic Discharge) coming through the antenna and helps with input matching. However, in the case of a passive balun used in general, since the AC signal is transmitted through electromagnetic coupling formed between two metal lines, it not only has loss without gain but also has the greatest influence on the total noise figure of the receiving end. Therefore, the design of a balun in a low-noise amplifier is very important, and it is important to design a balun in consideration of line width, line spacing, winding, radius, and layout symmetry that are necessary. In this paper, the factors to be considered for improving the quality factor of balun are summarized, and the tendency of variation of resistance, inductance, and capacitance of the balun according to design element change is analyzed. Based on the analysis results, it is proved that the design of input balun allows the design of low noise, high gain differential amplifier with gain of 24 dB and noise figure of 2.51 dB.

• Tribology and Lubricants
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• v.22 no.2
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• pp.59-65
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• 2006

In hard disk drives as the head to disk spacing continues to decrease to facilitate recording densities, slider disk interactions have become much more severe due to direct contact of head and disk surfaces in both start/stop and flying cases. The slider disk interaction in CSS (contact-start-stop) mode is an important source of particle generation and tribocharge build-up. The tribocharge build-up in the slider disk interface can cause ESD (electrostatic discharge) damage. In turn, ESD can cause severe melting damage to MR or GMR heads. The spindle speed of typical hard disk drives has increased in recent years from 5400 rpm to 15000 rpm and even higher speeds are anticipated in the near future. And the increasing disk velocity leads to increasing disk acceleration and this might affect the tribocharging phenomena of the slider/disk interface. We investigated the tribocurrent/voltage build-up generated in HDD, operating at increasing disk accelerations. In addition, we examined the effects with relative humidity conditions and rest time. We found that the tribocurrent/voltage was generated during pico-slider/disk interaction and its level was about $3\sim16pA$ and $0.1\sim0.3V$, respectively. Tribocurrent/voltage build-up was reduced with increasing disk acceleration. Higher humidity conditions $(75\sim80%)$ produced lower levels tribovoltage/current. Therefore, a higher tribocharge is expected at a lower disk acceleration and lower relative humidity condition. Rest time affected the charge build-up at the slider-disk interface. The degree of tribocharge build-up increased with increasing rest time.