• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.31-36
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• 2011

This paper investigates the ESD robustness of the stacked output driver with a 0.13um CMOS process. To represent an actual I/O system, we implemented stacked output driver circuits with pre-drivers and a rail-based power clamp. We implemented eight kinds of circuits varying pre-driver input connections and stacked driver size. The test circuits are examined with TLP measurements. It is shown that breakdown current and voltage can be increased by connecting the pre-driver input to a power supply and using stacked devices of a similar size. Based on the test results, design guideline is suggested to improve ESD robustness of the stacked output drivers.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.12
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• pp.68-76
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• 2015

We examine the standalone lightning warning system (LWS) and its warning performances for three years. This system acquires and analyzes the data of cloud-to-ground strike (CG), intra-cloud discharge (IC) and electrostatic field (EF) to produce prior warnings with respect to the impending arrival of CG in the area of concern (AOC). The warnings in this system are carried out based on the fixed two areas method. To evaluate warning performances, we analyzed the statistics of warnings with probability of detection (POD) and false alarm ratio (FAR). Based on the previous study, we revised the trigger and clear conditions of lightning warning for improving the performances of the system. As a result of this revision, POD increased from 0.18 to 0.44 and FAR decreased from 0.96 to 0.78 during the summer of 2014. However, the LWS was not possible to trigger effective alerts (EA) because there was no effective lead time (LT) for the fixed two areas method. Problems related to the low detection efficiency of IC and the use of EF data for warnings still decreased POD and increased FAR. Hence, we proposed the development method of a new LWS (NLWS) that would be composed of integrated weather data, the flexible two areas and the user software in order to trigger EA and improve warning performances.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.7
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• pp.1429-1435
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• 2004

In this work, high performance broadband amplifier MMIC including all the matching and biasing components, and electrostatic discharge (ESD) protection circuit was developed for K/Ka band applications. Therefore, external biasing or matching components were not required for the operation of the MMIC. STO (SrTiO3) capacitors were employed to integrate the DC biasing components on the MMIC, and miniaturized LC parallel ESD protection circuit was integrated on MMIC, which increased ESD breakdown voltage from 10 to 300 V. A pre-matching technique and RC parallel circuit were used for the broadband design of the amplifier MMIC. The amplifier MMIC exhibited good RF performances and good stability in a wide frequency range. The chip size of the MMICs was $1.7{\pm}0.8$ mm2.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.40-50
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• 2010

The studies of PMOS transistors in CMOS technologies are reviewed- focusing on the snapback and breakdown behavior of the parasitic PNP BJTs in high current regime. A new failure mechanism of PMOSFET devices under ESD conditions is also analyzed by investigating various I/O structures in a $0.13\;{\mu}m$ CMOS technology. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from the adjacent diodes into the body of the PMOSFET, significantly degrading the ESD robustness of PMOSFETs. Based on 2-D device simulations the critical layout parameters affecting this problem are identified. Design guidelines for avoiding this new PMOSFET failure mode are also suggested.

• Journal of IKEEE
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• v.19 no.2
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• pp.265-270
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• 2015

In this paper, we proposed a dual-directional SCR (silicon-controlled rectifier) based ESD (electrostatic discharge) protection circuit. In comparison with conventional SCR, this ESD protection circuit can provide an effective protection against ESD pulses in the two opposite directions, so the ESD protection circuit can be discharged in two opposite direction. The proposed circuit has a higher holding voltage characteristic than conventional SCR. These characteristic enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. it was analyzed to figure out electrical characteristics in term of individual design parameters. They are investigated by using the Synopsys TCAD simulator. In the simulation results, it has trigger voltage of 6.5V and holding voltage increased with different design parameters. The holding voltage of the proposed circuit changes from 2.1V to 6.3V and the proposed circuit has symmetrical I-V characteristic for positive and negative ESD pulse.

• Journal of IKEEE
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• v.15 no.4
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• pp.330-338
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• 2011

In this paper, a current-mode buck-boost converter using Multiple switching devices is presented. The efficiency of the proposed converter is higher than that of conventional buck-boost converter. In order to improve the power efficiency at the high current level, the proposed converter is controlled with PWM(pulse width modulation) method. The converter has maximum output current 300mA, input voltage 3.3V, output voltage from 700mV to 12V, 1.5MHz oscillation frequency, and maximum efficiency 90%. Moreover, this paper proposes watchdog circuits in order to ensure the reliability and to improve the performance of dc-dc converters. An electrostatic discharge(ESD) protection circuit for deep submicron CMOS technology is presented. The proposed circuit has low triggering voltage using gate-substrate biasing techniques. Simulated result shows that the proposed ESD protection circuit has lower triggering voltage(4.1V) than that of conventional ggNMOS(8.2V).

• Transactions on Electrical and Electronic Materials
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• v.17 no.4
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• pp.196-200
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• 2016

We have developed new electrostatic discharge (ESD) protection devices with, bidirectional flip chip transient voltage suppression. The devices differ in their epitaxial (epi) layers, which were grown by reduced pressure chemical vapor deposition (RPCVD). Their ESD properties were characterized using current-voltage (I-V), capacitance-voltage (C-V) measurement, and ESD analysis, including IEC61000-4-2, surge, and transmission line pulse (TLP) methods. Two BD-FCTVS diodes consisting of either a thick (12 μm) or thin (6 μm), n-Si epi layer showed the same reverse voltage of 8 V, very small reverse current level, and symmetric I-V and C-V curves. The damage found near the corner of the metal pads indicates that the size and shape of the radius governs their failure modes. The BD-FCTVS device made with a thin n- epi layer showed better performance than that made with a thick one in terms of enhancement of the features of ESD robustness, reliability, and protection capability. Therefore, this works confirms that the optimization of device parameters in conjunction with the doping concentration and thickness of epi layers be used to achieve high performance ESD properties.

• Tribology and Lubricants
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• v.22 no.2
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• pp.59-65
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• 2006

In hard disk drives as the head to disk spacing continues to decrease to facilitate recording densities, slider disk interactions have become much more severe due to direct contact of head and disk surfaces in both start/stop and flying cases. The slider disk interaction in CSS (contact-start-stop) mode is an important source of particle generation and tribocharge build-up. The tribocharge build-up in the slider disk interface can cause ESD (electrostatic discharge) damage. In turn, ESD can cause severe melting damage to MR or GMR heads. The spindle speed of typical hard disk drives has increased in recent years from 5400 rpm to 15000 rpm and even higher speeds are anticipated in the near future. And the increasing disk velocity leads to increasing disk acceleration and this might affect the tribocharging phenomena of the slider/disk interface. We investigated the tribocurrent/voltage build-up generated in HDD, operating at increasing disk accelerations. In addition, we examined the effects with relative humidity conditions and rest time. We found that the tribocurrent/voltage was generated during pico-slider/disk interaction and its level was about $3\sim16pA$ and $0.1\sim0.3V$, respectively. Tribocurrent/voltage build-up was reduced with increasing disk acceleration. Higher humidity conditions $(75\sim80%)$ produced lower levels tribovoltage/current. Therefore, a higher tribocharge is expected at a lower disk acceleration and lower relative humidity condition. Rest time affected the charge build-up at the slider-disk interface. The degree of tribocharge build-up increased with increasing rest time.

• Steel and Composite Structures
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• v.45 no.2
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• pp.205-218
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• 2022

Proper calculation of splitting tensile strength (STS) of concrete has been a crucial task, due to the wide use of concrete in the construction sector. Following many recent studies that have proposed various predictive models for this aim, this study suggests and tests the functionality of three hybrid models in predicting the STS from the characteristics of the mixture components including cement compressive strength, cement tensile strength, curing age, the maximum size of the crushed stone, stone powder content, sand fine modulus, water to binder ratio, and the ratio of sand. A multi-layer perceptron (MLP) neural network incorporates invasive weed optimization (IWO), cuttlefish optimization algorithm (CFOA), and electrostatic discharge algorithm (ESDA) which are among the newest optimization techniques. A dataset from the earlier literature is used for exploring and extrapolating the STS behavior. The results acquired from several accuracy criteria demonstrated a nice learning capability for all three hybrid models viz. IWO-MLP, CFOA-MLP, and ESDA-MLP. Also in the prediction phase, the prediction products were in a promising agreement (above 88%) with experimental results. However, a comparative look revealed the ESDA-MLP as the most accurate predictor. Considering mean absolute percentage error (MAPE) index, the error of ESDA-MLP was 9.05%, while the corresponding value for IWO-MLP and CFOA-MLP was 9.17 and 13.97%, respectively. Since the combination of MLP and ESDA can be an effective tool for optimizing the concrete mixture toward a desirable STS, the last part of this study is dedicated to extracting a predictive formula from this model.

• Journal of Electrical Engineering and Technology
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• v.12 no.5
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• pp.2021-2030
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• 2017

In this paper, the unipolar corona-needle charger was developed and its capabilities were both numerically and experimentally investigated. The experimental corona discharges and particle losses in the charger were obtained at different corona voltage, aerosol flow rate and particle diameter for positive and negative coronas. Inside the charger, the electric field and charge distribution and the transport behavior of the charged particle were predicted by a numerical simulation. The experimental results yielded the highest ion number concentrations of about $1.087{\times}10^{15}ions/m^3$ for a positive corona voltage of about 3.2 kV, and $1.247{\times}10^{16}ions/m^3$ for a negative corona voltage of about 2.9 kV, and the highest $N_it$ product for positive and negative coronas was found to about $7.53{\times}10^{13}$ and $8.65{\times}10^{14}ions/m^3$ s was occurred at the positive and negative corona voltages of about 3.2 and 2.9 kV, respectively, and the flow rate of 0.3 L/min. The highest diffusion loss was found to occur at particles with diameter of 30 nm to be about 62.50 and 19.33 % for the aerosol flow rate of 0.3 and 1.5 L/min, respectively, and the highest electrostatic loss was found to occur at particles with diameters of 75 and 50 nm to be about 86.29 and 72.92 % for positive and negative corona voltages of about 2.9 and 2.5 kV, respectively. The numerical results for the electric field distribution and the charged particles migration inside the charger were used to guide the description of the electric field and the behavior of charged particle trajectories to improve the design and refinement of a unipolar corona-needle charger that otherwise could not be seen from the experimental data.