• 전자공학회논문지B
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• 제30B권2호
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• pp.19-32
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• 1993

This paper suggests the new high-speed input/output techniques in a shared memory multiprocessor system. The high-speed I/O processor which can connect the different kinds of large sized I/O periperal devices, the communication protocol to the main processing units for I/O operations, and the job scheduling scheme are addressed. This paper also introduces the disk cache technique which supports the slow I/O devices comparing with the main processing units. These techniques were implemented in the TICOM system. The performance evaluation statistics were collected and analyzed for the suggested high-speed I/O processing techniques. These statistics show the superiority of the suggested techniques.

• 전자공학회논문지C
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• 제34C권5호
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• pp.1-17
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• 1997

With the increasing performance and density of VLSI scircuits as well as the popularity of portable devices such as personal digital assitance, power consumption has emerged as an important issue in the design of electronic systems. Low power design techniqeus have been pursued at all design levels. However, it is more effective to attempt to reduce power dissipation at higher levels of abstraction which allow wider view. In this paper, we propose a simultaneous scheduling and binding scheme which increases the correlation between cosecutive inputs to an operation so that the switched capacitance of execution units is reduced in datapath-dominated circuits. The proposed method is implemented and integrated into the scheduling and assignment part of HYPER synthesis environment. Compared with original HYPER synthesis system, average power saving of 23.0% in execution units and 14.2% in the whole circuits, ar eobtained for a set of benchmark examples.

• The Journal of the Acoustical Society of Korea
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• 제15권3E호
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• pp.60-65
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• 1996

This paper describes on the Korean continuous speech recognition system for flight reservation. It adopts a frame-synchronous One-Pass DP search algorithm driven by syntactic constraints of context free grammar(CFG). For recognition, 48 phoneme-like units(PLU) were defined and used as basic units for acoustic modeling of Korean. This modeling was conducted using a HMM technique, where each model has 4-states 3-continuous output probability distributions and 3-discrete-duration distributions. Language modeling by CFG was also applied to the task domain of flight reservation, which consisted of 346 words and 422 rewriting rules. In the tests, the sentence recognition rate of 62.6% was obtained after speaker adaptation.

• 한국항공우주학회지
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• 제35권3호
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• pp.268-274
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• 2007

일반적으로 로켓과 위성 전자 회로 설계 단계에서 전자 소자의 신뢰도를 높이기 위해 소자의 작동온도를 낮추는 방법이 많이 사용된다. 본 논문에서는 소자 온도뿐 아니라 활성화에너지가 전자 장비 신뢰도에 미치는 영향에 대해 상세히 분석하였는데 실제 소자의 온도보다는 소자의 활성화에너지가 신뢰도에 훨씬 많은 영향을 끼치는 것으로 분석되었으며 이에 대한 분석결과를 정량적으로 기술하였다. 또한 PCB에 소자 배치 시 신뢰도를 높이기 위한 소자 배치 방법과 이에 따른 신뢰도 향상 결과에 대해서도 기술하였다.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2006년도 한국컴퓨터종합학술대회 논문집 Vol.33 No.1 (B)
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• pp.307-309
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• 2006

움직이는 오브젝트(Object)를 추출하기 위한 배경 제거(Background Subtraction) 단계는 실시간 감시시스템(Real-time Surveillance System)에서 중요한 과정 중에 하나이다. 배경 제거를 효과적으로 진행하기 위한 배경을 모델링, 배경 유지 보수 방법이 존재하는데, 효율성이 높은 방법으로 적응적 가우시안 혼합 배경 모델링(Adaptive Gaussian Mixture Background Modeling)이 제시되고 있다. 본 논문에서는 이기법을 바탕으로 하여 이러한 실시간 배경 모델링 시스템을 구현하려 하고, 중앙 처리 장치(CPU)가 아닌 그래픽 처리 장치(Graphic Processing Units : GPU)를 사용하여 보다 향상된 방범을 구현함으로서 관련사항을 제안하려 한다.

• 한국지능시스템학회논문지
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• 제18권3호
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• pp.323-328
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• 2008

본 논문에서는 연산 중심의 DSP 작업에 대한 성능을 유지하면서 제어 작업을 효과적으로 수행할 수 있는 프로세서 구조를 제안하고 구현하였다. 전통적으로 DSP작업은 직렬 연결된 연산기로 구현되지만, 제안한 프로세서에서는 곱셈기, 2개의 ALU, 읽기/쓰기 유닛 등 4개의 실행 유닛이 병렬로 배치되어 있고 수퍼스칼라 방식으로 제어되므로 동시에 처리된다. 제안된 프로세서를 사용하여 AC-3 오디오 복호화기를 구현하여 성능이 37.8% 향상됨을 확인하였다. 이와 같은 연구는 기존의 고성능 DSP를 사용할 수 없는 저가격의 가전기기용 부품제작에 활용이 가능하다.

• 대한전자공학회논문지SD
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• 제46권3호
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• pp.20-25
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• 2009

본 논문에서는 모바일 환경 기반의 3차원 그래픽 연산을 위한 조명처리 엔진 및 쉐이더 프로세서에 사용 가능한 제곱근과 역제곱근 연산기의 구조를 제안한다. 제안하는 구조는 Taylor 전개식을 기반으로 하여 참조 테이블 및 보정 유닛으로 구성되어 있어 참조 테이블의 크기를 줄였다. 연산 결과는 IEEE-754 표준의 단정도 32 bit 부동소수점 형식과 모바일 환경을 위하여 이를 축소한 24 bit 부동소수점 형식에 대해 OpenGL 1.x ES 에서 요구하는 $10^{-5}$의 정확도를 거의 만족한다. 제안된 구조에 따라 설계된 제곱근 및 역제곱근 연산기는 Verilog-HDL을 사용하여 설계되었으며 파라미터 변경을 통하여 24 bit와 32 bit 연산이 가능하도록 합성이 가능하고 1사이클의 잠복기를 갖는다. 설계된 연산기들의 동작은 FPGA를 이용한 검증시스템을 통하여 검증하였다.

• 전기학회논문지
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• 제66권6호
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• pp.955-961
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• 2017

In this paper, we propose a parallel approximate string matching algorithm with k-mismatches for multiple fixed-length patterns (PMASM) in DNA sequences. PMASM is developed from parallel single pattern approximate string matching algorithms to effectively calculate the Hamming distances for multiple patterns with a fixed-length. In the preprocessing phase of PMASM, all target patterns are binary encoded and stored into a look-up memory. With each input character from the input string, the Hamming distances between a substring and all patterns can be updated at the same time based on the binary encoding information in the look-up memory. Moreover, PMASM adopts graphics processing units (GPUs) to process the data computations in parallel. This paper presents three kinds of PMASM implementation methods in GPUs: thread PMASM, block-thread PMASM, and shared-mem PMASM methods. The shared-mem PMASM method gives an example to effectively make use of the GPU parallel capacity. Moreover, it also exploits special features of the CUDA (Compute Unified Device Architecture) memory structure to optimize the performance. In the experiments with DNA sequences, the proposed PMASM on GPU is 385, 77, and 64 times faster than the traditional naive algorithm, the shift-add algorithm and the single thread PMASM implementation on CPU. With the same NVIDIA GPU model, the performance of the proposed approach is enhanced up to 44% and 21%, compared with the naive, and the shift-add algorithms.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.258-261
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• 2002

This paper addresses the problem of merging two feedforward neural networks into one network. Merging is accomplished at the level of hidden layer. A new network selects its hidden layer's units from the two networks to be merged We uses information theoretic criterion (quadratic mutual information) in the selection process. The hidden unit's output and the target patterns are considers as random variables and the mutual information between them is calculated. The mutual information between hidden units are also considered to prevent the statistically dependent units from being selected. Because mutual information is invariant under linear transformation of the variables, it shows the property of the robust estimation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.715-718
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• 2005

Mobile devices is getting to include more functions according to the demand of digital convergence. Applications based on 3D graphic calculation such as 3D games and navigation are one of the functions. 3D graphic calculation requires heavy calculation. Therefore, we need dedicated 3D graphic hardware unit with high performance. 3D graphic calculation needs a lot of complicated floating-point arithmetic operation. However, most of current mobile 3D graphics processors do not have efficient architecture for mobile devices because they are based on those for conventional computer systems. In this paper, we propose arithmetic units for special functions of lighting operation of 3D graphics. Transcendental arithmetic units are designed using approximation of logarithm function. Special function units for lighting operation such as reciprocal, square root, reciprocal of square root, and power can be obtained. The proposed arithmetic unit has lower error rate and smaller silicon area than conventional arithmetic architecture.