• Journal of the Institute of Electronics Engineers of Korea SC
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• v.42 no.3 s.303
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• pp.33-40
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• 2005

In order to successfully exploit underwater resources, the first step would be a marine environmental research and exploration on the seafloor. Traditionally one sets up a long-term underwater experimental unit on the seafloor and retrieves the unit later after a certain period time. Essential to these applications is the reliable teleoperation and telemetering of the unit. This study presents ultrasonic-wave remote control system and an underwater sound recognition algorithm that can identify the sound signal without the influence of disturbances due to underwater environmental changes. The proposed method provides a means suitable for units which require low power dissipation and long-time underwater operation. We demonstrate its ability of securing stability and fast sound recognition through experimental methods.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.135-141
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• 2013

In this paper, we installed three high brightness red, green, and blue LED in one socket and made one pixel unit. And we also developed the full-color display board module and control unit which can express various images such as text, graphics, video image with the combination of pixel units and a number of modules. LED display driver module have a driver circuit within the combination of the RGB pixel dot on unit area. These modules of the existing form can be high priced because of implementation a fixed resolution in specific space and installation space. To overcome these shortcomings, we developed a LED driver and LED pixel modules free in array at random pitch intervals. Display board module of this paper enabled to display smoothly video image which have many data processing quantity through dragging data speed up 36 frames per second. Also there are an effect which is provided more clear image because of improving the flickering of the existing display board.

• Journal of IKEEE
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• v.3 no.2 s.5
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• pp.186-195
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• 1999

In this paper, the RF-modules composed of front-end, frequency synthesizer, modulator/demodulator and power control multi channel WLL personal system for W-CDMA using 10 [MHz] RF channel bandwidth has been implemented and considered. The measured transmission power is 250 [mW] which is very close to the required value. The measured flatness of power at the final output stage is ${\pm}1.5[dB]$ over the required bandwidth of the receiver. In addition, it is found that the chip rate transmitting spread signal is set to 8.192 [MHz], the required rate. The frequencies of RF_LO signal and LO signal of the modulator and the demodulator measured by a frequency synthesizer are satisfied with design requirements. The operating range of the receiving strength signal indicator and AGC units shows 60 [dB] respectively. Also the measured phasor diagram and eye pattern for deciding the RF modules compatible with baseband digital signal processing part are shown good results.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.11
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• pp.75-83
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• 1999

We propose a PfSGA(parameter-free species genetic algorithm) to learn the topological structure of MLP classifiers being adequate to given applications. The PfSGA is a combinational method of SGA(species genetic algorithm) and PfGA(parameter-free genetic algorithm). In SGA, we divide the total search space into several subspaces(species) according to the number of hidden units, and reduce the unnecessary search by eliminating the low promising species from the evolutionary process. However the performances of SGA classifiers are readily affected by the values of parameters such as mutation ratio and crossover ratio. In this paper, therefore, we combine SGA with PfGA, for which it is not necessary to determine the learning parameters. Experimental results on benchmark data and sign language words show that PfSGA can reduce the learning time of SGA and is not affected by the selection parameter values on structural learning. The results also show that PfSGA is more efficient than the exisiting methods in the aspect of misclassification ratio, learning rate, and complexity of MLP structure.

• Transactions of the Korean Society for Noise and Vibration Engineering
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• v.26 no.5
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• pp.536-545
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• 2016

Household refrigerator radiates noise of which the pattern is dependent on the operating condition of its parts, such as compressor, flow fans, etc. Thus the refrigerator noise has a variety of frequency characteristics. Therefore, it is required to consider the noise characteristics for evaluating the noise quality and eventually developing the sound quality index of the refrigerator noise. In this study, five units of household refrigerator were selected to measure their noises that were used to generate sound sources for jury test of the study. The measured noises of five refrigerators were divided into ten kinds of sound source by considering operating condition and frequency characteristics. Additionally, the ten sources were each edited to have the same SPL of 30 dBA. Totally twenty kinds of sound sources (10-original SPL, 10-edited SPL 30 dBA) were evaluated by twenty-two subjects, and compared with their sound quality metrics. It was found that only the loudness of the metrics was meaningfully correlated with the subjective evaluation. The rests, sharpness, roughness and fluctuation strength, were not related. The conclusion of this study is that a new sophisticated index is necessary to be developed to qualitatively evaluate the household refrigerator noise.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.67-74
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• 2005

Crypto-systems have difficulties in designing hardware due to the various standards. We propose a programmable and configurable architecture for cryptography coprocessors to accommodate various crypto-systems. The proposed architecture has a 32 bit I/O interface and internal bus width, and consists of a programmable finite field arithmetic unit, an input/output unit, a register file, and a control unit. The crypto-system is determined by the micro-codes in memory of the control unit, and is configured by programming the micro-codes. The coprocessor has a modular structure so that the arithmetic unit can be replaced if a substitute has an appropriate 32 bit I/O interface. It can be used in many crypto-systems by re-programming the micro-codes for corresponding crypto-system or by replacing operation units. We implement an elliptic curve crypto-processor using the proposed architecture and compare it with other crypto-processors

• Journal of the Korean association of regional geographers
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• v.8 no.4
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• pp.529-541
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• 2002

This paper aims to provide a context-specific interpretation on the shifting process of in-house R&D spaces in a large Korean firm in the context of rapidly changing markets and technology. Drawing on the case study of LG Electronics Company, one of the Korea's flagship companies, I examine the causes and mechanisms leading to a shift in domestic R&D spaces and the nature of learning processes between R&D teams and between R&D and other organizational units, particularly manufacturing. It appears that the current reshaping processes of domestic R&D spaces in LGE focus more on the clustering of core R&D laboratories than the geographical integration of conception and execution. However, it should not simply be viewed that such a move would be reduced to the linear model of innovation and organizational learning. Instead, it involves the firm-specific mode of regulating organizational competences. As contextual variables to induce such a firm-specific mode of organizational change, I consider the spatial form of organization, the spatial sources of knowledge and learning, and the powers of relational learning that can be made between distanciated actors and teams.

• Journal of the Korean Society for Precision Engineering
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• v.28 no.10
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• pp.1131-1140
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• 2011

A new rotary gravure-offset printing unit is constructed by paralleling a gravure plate cylinder, a blanket cylinder and a impression roller. A Muti-Unit Gravure-Offset Printing Press(MUGOP) equipped with a series of the 3 printing units is utilized for roll-to-roll fine printing. Its core technology is precise over-piling printing of fine patterns. The severe problems of 'slurring' and 'doubling' in typical offset printing are unavoidable, which can be eliminated by applying a soft pad-type blanket cylinder and the unique 'true rolling' technique. Nip pressure between the blanket cylinder and the plate cylinder is measured by the constant pressure control system which equipped with load cells attached on the cylinders' axes. The running circumference of the blanket cylinder is increased to reach the same circumference of the plate cylinder as the pressure increasing, so that the specifications of the blanket cylinder is determined by the relationships of its shore hardness, diameter and nip pressure. When a softer blanket is used, a blanket cylinder of smaller diameter could give higher nip pressure. Realization of the true rolling technique on the MUGOP makes multilayer printing possible as well as fine printing in printed electronics.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.9
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• pp.1115-1124
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• 1988

A two-dimensional systolic array for fast Fourier transform, which has a regular and recursive VLSI architecture is presented. The array is constructed with identical processing elements (PE) in mesh type, and due to its modularity, it can be expanded to an arbitrary size. A processing element consists of two data routing units, a butterfly arithmetic unit and a simple control unit. The array computes FFT through three procedures` I/O pipelining, data shuffling and butterfly arithmetic. By utilizing parallelism, pipelining and local communication geometry during data movement, the two-dimensional systolic array eliminates global and irregular commutation problems, which have been a limiting factor in VLSI implementation of FFT processor. The systolic array executes a half butterfly arithmetic based on a distributed arithmetic that can carry out multiplication with only adders. Also, the systolic array provides 100% PE activity, i.e., none of the PEs are idle at any time. A chip for half butterfly arithmetic, which consists of two BLC adders and registers, has been fabricated using a 3-um single metal P-well CMOS technology. With the half butterfly arithmetic execution time of about 500 ns which has been obtained b critical path delay simulation, totla FFT execution time for 1024 points is estimated about 16.6 us at clock frequency of 20MHz. A one-PE chip expnsible to anly size of array is being fabricated using a 2-um, double metal, P-well CMOS process. The chip was layouted using standard cell library and macrocell of BLC adder with the aid of auto-routing software. It consists of around 6000 transistors and 68 I/O pads on 3.4x2.8mm\ulcornerarea. A built-i self-testing circuit, BILBO (Built-In Logic Block Observation), was employed at the expense of 3% hardware overhead.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.39 no.5
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• pp.32-44
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• 2002

In this paper, we propose TV caption-based KSL(Korean Sign Language) generation system. Through TV caption decoder, this caption signal is transmitted to PC. Next, caption signal is segmented into meaning units by morphological analyzer in considering specific characteristics of Korean sign language. Finally, 3D KSL generation system represents the transformed morphological information by 3D visual graphics. Specifically, we propose a morphological analyzer with many pre-processing techniques for real-time capability. Our developed system is applied to real TV caption program. Through usage of the deaf, we conclude that our system is sufficiently usable compared to conventional TV caption program.