• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 전력전자학술대회
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• pp.271-272
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• 2011

The rising popularity of renewable energy sources resulted in development of the units of higher rated powers. As a result of the limited power handling capacity of individual devices, paralleling is the choice to increase the equipment rating, while keeping the THD of the current at the PCC within the agency specified standards. And their typical power circuit configuration limits the stress on individual devices to an appreciable extent. The main scope of this paper is the analysis of filter structure in paralleling inverter system's operation. Simulation results are shown to verify the theoretical analysis.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.929-932
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• 1998

In this paper we propose a method of representing emotional experessions and lip shapes for sign language communication using 3-dimensional model. At first we employ the action units (AU) of facial action coding system(FACS) to display all shapes. Then we define 11 basic lip shapes and sounding times of each components in a syllable in order to synthesize the lip shapes more precisely for korean characters. Experimental results show that the proposed method could be used efficiently for the sign language image communication between different languages.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.153-156
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• 2001

This paper analyzes the 74LS381 ALU and designs its equivalent circuit. The 74LS381 ALU is arithmetic logic units(ALUs)/function generators that perform eight binary arithmetic/logic operations on two 4-bit words. However there are only little information to understand and design this circuit. Thus, we not only analyzed it but also designed an equivalent circuit to the 74LS381.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.75-78
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• 2000

This paper presents a new algorithm for allocating the data path to achieve the minimum power consumption under the constraints of minimum hardware resources. In order to minimize the power consumption, the proposed algorithm tries to minimize the input transitions of functional units, unnecessary computations, and size of interconnects in a greedy manner during a]location. Experimental results using benchmarks indicate the proposed algorithm achieves 17.5% power reduction on average, when compared with the genesis-lp［1］high-level synthesis system.

• ETRI Journal
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• 제10권4호
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• pp.89-98
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• 1988

We consider an N duplicate-server system, where each server consists of two reconfigurable duplicated units which are subject to breakdowns. This system is studied analytically using generating functions, and also numerically using the matrix-geometric procedure. Using the generating function approach we obtain a recursive expression of the queuelength distribution for N=1. This expression in difficult to generalize to N>1. The numerical method is applicable for any value of N. For any N, we also obtain the condition for stability and the availability of the system.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.199-202
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• 1999

In this paper, a possibility of building various types of RF passive components using the silicon micromachining technique has been examined with special emphasis on the wireless and mobile communication applications. Silicon micromachining technique is compatible with conventional silicon IC process and could provide a possibility of integrating base-band signal processing units and RF passive and active circuit components all in one silicon wafer rendering implementation of system-on-chip paradigm for future mobile and wireless communication systems.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 Ⅳ
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• pp.2240-2243
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• 2003

In this paper. we present a new speech recognition system using DSP chip. DSP chip used TMS320c6711 of TI. We designed hardware system including acoustic model, word list and code book in flash memory. The word candidates are recognized based on CV, VCCV, and VC units HMM. This system can be applied to various electric ＆ electronic devices: home automation, robotics etc.

• 한국통신학회논문지
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• 제26권8B호
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• pp.1078-1084
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• 2001

In this paper, fuzzy-ARTMAP neural network is applied for compensating the nonlinearity of satellite communication channel. The fuzzy-ARTMAP is made of using fuzzy logic and ART neural network. By a match tracking process with vigilance parameter, fuzzy ARTMAP neural network achieves a minimax learning rule that minimizes predictive error and maximizes generalization. Thus, the system automatically learns a minimal number of recognition categories, or hidden units, to meet accuracy criteria. Simulation studies are performed over satellite nonlinear channels. The performance of proposed fuzzy-ARTMAP equalizer is compared with MLP-basis equalizers.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.989-990
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• 2006

This paper presents a design of 3D Graphics Geometry processor. A geometry processor needs to cope with a large amount of computation and consists of transformation processor and lighting processor. To deal with the huge computation, a vector processing structure based on pipeline chaining is proposed. The proposed geometry processor performs 4.3M vertices/sec at 100MHz using 11 floating-point units.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -2
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• pp.657-660
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• 2000

This paper proposes a Data-Flow-Graph (DFG) restructuring to reduce calculating errors in loop folding scheduling. The prime cause of calculating error is rounding errors due to the restriction of the operation digit of functional units. This rounding error is increased more by using multipliers than adders, so reducing the number of multiplications and putting off them as much as possible reduce rounding errors. The proposed approach reduces the number of multiplications by restructuring DFG in loop folding.