• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.2
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• pp.152-155
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• 2011

Even though nano-scale materials were very advantageous for various applications, there are still problems to be solved such as the stabilization of surface state and realization of low contact resistances between a semiconducting nanowire and electrodes in nano-electronics. It is well known that the effects of contacts barrier between nano-channel and metal electrodes were dominant in carrier transportation in individual nano-electronics. In this report, it was investigated the electrical properties of GaN nanorod devices after chemical etching and rapid thermal annealing for making good contacts. After KOH wet-etching of the contact area the devices showed better electrical performance compared with non-treated GaN individual devices but still didn't have linear voltage-current characteristics. The shape of voltage-current properties of GaN devices were improved remarkably after rapid thermal annealing as showing Ohmic behaviors with further bigger conductivities. Even though chemical etching of the nanorod surfaces could cause scattering of carriers, in here it was shown that the most important and dominant factor in carrier transport of nano-electronics was realization of low contact barrier between nano-channel and metal electrodes surely.

• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.139-142
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• 2013

Silicon nanowire (SiNW) silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices were fabricated and their electrical characteristics were analyzed. Compared to planar SONOS devices, these SiNW SONOS devices have good program/erase (P/E) characteristics and a large threshold voltage ($V_T$) shift of 2.5 V in 1ms using a gate pulse of +14 V. The devices also show excellent immunity to short channel effects (SCEs) due to enhanced gate controllability, which becomes more apparent as the nanowire width decreases. This is attributed to the fully depleted mode operation as the nanowire becomes narrower. 3D TCAD simulations of both devices show that the electric field of the junction area is significantly reduced in the SiNW structure.

• Transactions on Electrical and Electronic Materials
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• v.6 no.5
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• pp.238-242
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• 2005

The Pt counter electrode of a dye-sensitized solar cell (DSSC) plays a role in helping redox reaction of iodine ions in electrolyte, also, transferring electrons into electrolyte. In this case, it is expected that characteristics of Pt electrodes strongly depend on fabrication process and its surface condition. In this study, Pt electrodes were prepared by a electro-deposition and a RF magnetron sputtering. Electrochemical behavior of Pt electrodes was compared using cyclic-voltammetry and impedance spectroscopy. Surface morphology of Pt electrodes was investigated by FE-SEM and AFM. I-V characteristics of DSSC were measured and discussed in association with the surface properties of counter electrode. As a result, electrochemical properties of electro-deposited Pt electrode were superior to that of sputtered Pt electrode. This is likely that enlarged area of surface in electro-deposited Pt electrode in comparison with the case of sputtered Pt electrode playa role in enhancing such electrochemical properties.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.687-690
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• 2004

Fabrication and characterization of dye-sensitized TiO2 solar cells(DSSC) consisting of spray-coated TiO2 electrode, an electrolyte containing I-/I3- redox couple, and a Pt-coated counter electrode carried out, using mainly FE-SEM and solar simulator. Also, effect of rapid thermal annealing(RTA) temperatue on I-V curves of DSSCS consisting of approximately 10m thickness and $5{\times}5mm2$ active area. No significant difference in the apparent size of TiO2 clusters was observed with increasing RTA temperature. Also, an open circuit voltage(Voc) of approximately 0.70V and a short-circuit photocurrent(Jsc) of 8 to 12mA/cm2 were observed in the TiO2 solar cell. With increasing RTA temperature upto 550oC, photocurrent density of dye-sensitized solar cells was enhanced, leading to enhancing the efficiency of dye-sensitized solar cells having Pt-electroplated counter electrode.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.331-334
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• 2000

The organic electroluminescent(EL) device has gathered much interest because of its large potential in materials and simple device fabrication. We fabricated EL devices which have a blended single emitting layer containg poly(Nvinylcarbazole)[PVK] and poly(3-dodecylthiophene)[P3DoDT]. The molar ratio between P3DoDT and PVK changed with 1:0, 2:1 and 1:1. To improve the external quantum efficiency of EL devices, we applied insulating layer, LiF layer between polymer emitting layer and AI electrode. All of the devices emit orange-red light and it's can be explained that the energy transfer occurs from PVK to P3DoDT. Within the molar ratio 1:0, 2:1 and 1:1, the energy transfer was not saturated, which results in the not appearance of PVK emission in the blue region. In the voltage-current and voltage-light power characteristics of devices applied LiF layer, current and light power drastically increased with increasing with applied voltage. In the consequence of the result, the light power of the device have a molar ratio 1:1 with LiF layer was about 10 times larger than that of the device without PVK at 6V.

• Transactions on Electrical and Electronic Materials
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• v.11 no.3
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• pp.93-105
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• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.193-193
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• 2008

Wearable and ubiquitous micro systems will be greatly growing and their related devices should be self-powered in order to avoid the replacement of finite power sources, for example, by scavenging energy from the environment. With ever reducing power requirements of both analog and digital circuits, power scavenging approaches are becoming increasingly realistic. One approach is to drive an electromechanical converter from ambient motion or vibration. Vibration-driven generators based on electromagnetic, electrostatic and piezoelectric technologies have been demonstrated. Among various generator types proposed so far, piezoelectric generator possesses considerable potential in micro system. To overcome low mechanical-to-electric energy conversion, the piezoelectric device should activate in resonance mode in response to external vibration. Normally, the external vibration excretes at low frequency ranging 0.1 to 200 Hz, whereas the resonant frequencies of the devices are fixed as constant. Therefore, keeping their resonant mode in varying external vibration can be one of important points in enhancing the conversion efficiency. We investigated the possibility of use of multi-bender type piezoelectric devices. To match the external vibration frequency with the device resonant frequency, the various devices with different resonant frequency were chosen.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.05c
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• pp.253-256
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• 2003

This study presents the combined effect of electric field application and mechanical compressive stress loading on deformation in a multilayer ceramic actuator, designed with stacking alternatively $0.2(PbMn_{1/3}Nb_{2/3}O_3)-0.8(PbZr_{0.475}Ti_{0.525}O_3)$ ceramics and Ag-Pd electrode. The deformation behaviors were thought to be attributed to relative $180^{\circ}$domain quantities which is determined by pre-loaded stress and electric field. The non-linearity of piezoelectricity and strain are dependent upon the young's modulus resulting from the domain reorientation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.4
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• pp.208-211
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• 2018

This paper details the design of a 1,200 V class trench gate field stop IGBT (insulated gate bipolar transistor) with a nano gate structure smaller than 1 um. Decreasing the size is important for lowering the cost and increasing the efficiency of power devices because they are high-voltage switching devices, unlike memory devices. Therefore, in this paper, we used a 2-D device and process simulations to maintain a gate width of less than 1 um, and carried out experiments to determine design and process parameters to optimize the core electrical characteristics, such as breakdown voltage and on-state voltage drop. As a result of these experiments, we obtained a wafer resistivity of $45{\Omega}{\cdot}cm$, a drift layer depth of more than 180 um, an N+ buffer resistivity of 0.08, and an N+ buffer thickness of 0.5 um, which are important for maintaining 1,200 V class IGBTs. Specially, it is more important to optimize the resistivity of the wafer than the depth of the drift layer to maintain a high breakdown voltage for these devices.

• Electrical & Electronic Materials
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• v.10 no.6
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• pp.589-607
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• 1997