• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Korean Journal of Materials Research
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• v.8 no.12
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• pp.1182-1189
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• 1998

High quality $TiN/TiSi_2$-bilayers were formed on the Si(100) substrate at room temperature and at $600^{\circ}C$ first by coevaporation of stoichiometric Si and Ti(Si:Ti = 2:1) fellowed by Ti reactive deposition in N, gas ambient, and in situ annealing in ultrahigh vacuum. Stoichiometric $Ti_{0.}N_{0.5}$, films with (111) texture and $C54-TiSi_2$ films were grown by annealing at temperatures above $700^{\circ}C$. $TiN/C54-TiSi_2$/Si(100) interface was clear and flat without agglomoration, and $CS4-TiSi_2$ film was epitxailly grown. The sheet resistance of the $TiN/TiSi_2$- bilayer decreased as the annealing temperature increased and about $2.5\omega/\textrm{cm}^2$ was obtained from the sample annealed over $700^{\circ}C$.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.4
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• pp.29-34
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• 2008

Generally, for conventional 3-D Hall sensor it is general that the sensitivity for $B_z$ is about 1/10 compared with those for $B_x$ or $B_y$. Therefore, in this work, we proposed 3-D Hall sensor with new structures. We have increased the sensitivity about 6 times to form the trench using anisotropic etching. And we have increased the sensitivity for the $B_z$ by 80 % compared with those of $B_x$ and $B_y$ using deposition of the ferromagnetic thin films on the bottom surface of the wafer to concentrate the magnetic fluxes. Sensitivities of the fabricated sensor with Ni/Fe film for $B_x,\;B_y$, and $B_z$ were measured as 361mV/T, 335mV/T, and 286mV/T, respectively. It has also showed sine wave of Hall voltages over a $360^{\circ}$ rotation. A packaged sensing part was $1.2{\times}1.2mm^2$. The measured linearity of the sensor was within ${\pm}3%$ of error. Resolution of the fabricated sensor was measured by $1{\times}10^{-5}T$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.62-62
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• 2008

As micro-system move toward higher speed and miniaturization, requirements for embedding the passive components into printed circuit boards (PCBs) grow consistently. They should be fabricated in smaller size with maintaining and even improving the overall performance. Miniaturization potential steps from the replacement of surface-mount components and the subsequent reduction of the required wiring-board real estate. Among the embedded passive components, capacitors are most widely studied because they are the major components in terms of size and number. Embedding of passive components such as capacitors into polymer-based PCB is becoming an important strategy for electronics miniaturization, device reliability, and manufacturing cost reduction Now days, the dielectric films deposited directly on the polymer substrate are also studied widely. The processing temperature below $200^{\circ}C$ is required for polymer substrates. For a low temperature deposition, bismuth-based pyrochlore materials are known as promising candidate for capacitor $B_2Mg_{2/3}Nb_{4/3}O_7$ ($B_2MN$) multi layers were deposited on Pt/$TiO_2/SiO_2$/Si substrates by radio frequency magnetron sputtering system at room temperature. The physical and structural properties of them are investigated by SEM, AFM, TEM, XPS. The dielectric properties of MIM structured capacitors were evaluated by impedance analyzer (Agilent HP4194A). The leakage current characteristics of MIM structured capacitor were measured by semiconductor parameter analysis (Agilent HP4145B). 200 nm-thick $B_2MN$ muti layer were deposited at room temperature had capacitance density about $1{\mu}F/cm^2$ at 100kHz, dissipation factor of < 1% and dielectric constant of > 100 at 100kHz.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.477-477
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• 2008

For more than three decades, the gate dielectrics in CMOS devices are $SiO_2$ because of its blocking properties of current in insulated gate FET channels. As the dimensions of feature size have been scaled down (width and the thickness is reduced down to 50 urn and 2 urn or less), gate leakage current is increased and reliability of $SiO_2$ is reduced. Many metal oxides such as $TiO_2$, $Ta_2O_4$, $SrTiO_3$, $Al_2O_3$, $HfO_2$ and $ZrO_2$ have been challenged for memory devices. These materials posses relatively high dielectric constant, but $HfO_2$ and $Al_2O_3$ did not provide sufficient advantages over $SiO_2$ or $Si_3N_4$ because of reaction with Si substrate. Recently, $HfO_2$ have been attracted attention because Hf forms the most stable oxide with the highest heat of formation. In addition, Hf can reduce the native oxide layer by creating $HfO_2$. However, new gate oxide candidates must satisfy a standard CMOS process. In order to fabricate high density memories with small feature size, the plasma etch process should be developed by well understanding and optimizing plasma behaviors. Therefore, it is necessary that the etch behavior of $HfO_2$ and plasma parameters are systematically investigated as functions of process parameters including gas mixing ratio, rf power, pressure and temperature to determine the mechanism of plasma induced damage. However, there is few studies on the the etch mechanism and the surface reactions in $BCl_3$ based plasma to etch $HfO_2$ thin films. In this work, the samples of $HfO_2$ were prepared on Si wafer with using atomic layer deposition. In our previous work, the maximum etch rate of $BCl_3$/Ar were obtained 20% $BCl_3$/ 80% Ar. Over 20% $BCl_3$ addition, the etch rate of $HfO_2$ decreased. The etching rate of $HfO_2$ and selectivity of $HfO_2$ to Si were investigated with using in inductively coupled plasma etching system (ICP) and $BCl_3/Cl_2$/Ar plasma. The change of volume densities of radical and atoms were monitored with using optical emission spectroscopy analysis (OES). The variations of components of etched surfaces for $HfO_2$ was investigated with using x-ray photo electron spectroscopy (XPS). In order to investigate the accumulation of etch by products during etch process, the exposed surface of $HfO_2$ in $BCl_3/Cl_2$/Ar plasma was compared with surface of as-doped $HfO_2$ and all the surfaces of samples were examined with field emission scanning electron microscopy and atomic force microscope (AFM).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.20-20
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• 2008

최근 LEDs가 동일 효율의 전구에 비해 에너지 절감 효과 크며 신뢰성이 뛰어나다기 때문에 기존 광원을 빠르게 대체해 나가고 있다. 특히 자외선 파장을 가지는 LEDs는 발열이 낮아 냉각장치가 필요 없으며, 수명이 길어 기존 UV lamp에 비해 많은 장점을 가지고 있기 때문에 많은 관심을 밭고 있다. 그럼에도 불구하고 자외선 LEDs는 제조 단가가 높고 power가 낮아 소요량이 많은 등 아직 해결해야 할 부분이 많기 때문에 이를 해결하기 위해 여러가지 재료와 다양한 구조가 고려되고 있다. 그 중 ZnO는 II-VI족 화합물 반도체로써 UV영역의 넓은 밴드갭(3.37eV)을 가지는 투명한 재료이다. 특히 ZnO는 60meV의 큰 엑시톤 결합에너지를 가지며, 가시광 영역에서 높은 투과율을 가지고, 상온에서 물리적, 화학적으로 안정하기 때문에 UV sensor, UV laser, UV converter, UV LEDs 등 광소자 분야에서 연구가 활발히 진행되고 있다. ZnO가 광소자의 발광재료로써 높은 효율을 얻기 위해서는 결정성을 높여 내부 결함을 감소시키며, 발광 면적을 높일 수 있는 구조가 요구된다. 특히 MOCVD 법으로 성장한 나노막대는 에피성장되어 높은 결정성을 기대할 수 있으며, 성장 조건을 조절함으로써 나노막대의 aspect ratio와 밀도 제어할 수 있기 때문에 표면적을 효과적으로 넓혀 높은 발광효율을 얻을 수 있다. 본 실험에서는 MOCVD 법으로 실리콘과 사파이어 기판 위에 다양한 성장 온도를 가진 나노구조를 성장 시키고 온도에 따른 형상 변화와 특성을 평가하였다. ZnO 의 성장온도가 약 $360^{\circ}C$ 일 때, 밀도가 조밀하고 기판에 수직 배열한 균일한 나노막대가 성장되었으며 우수한 결정성, 광학적 특성이 나타남을 SEM, TEM, PL, XRD를 사용하여 확인하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.41-41
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• 2007

For use in spintronic materials, dilute magnetic semiconductors (DMS) are under consideration as spin injectors for spintronic devices[l]. $TiO_2$-based DMS doped by a cobalt, iron, and manganese et al. was recently reported to show ferromagnetic properties, even at temperatures above 300K and the magnetic ordering was explained in terms of carrier-induced ferromagnetism, as observed for a III-V based DMS. An anomalous Hall effect (AHE) and co-occurance of superparamagnetism in reduced Co-doped rutile $TiO_{2-\delta}$ films have also been reported[2]. Metal segregation in the reduced metal-doped rutile $TiO_2-\delta$ films still remains as problems to solve the intrinsic DMS properties. Superlattice films have been proposed to get dilute magnetic semiconductor (DMS) with intrinsicroom-temperature ferromagnetism. For a $TiO_2$-based DMS superlattice structure, each layer was alternately doped by two different transition metals (Fe and Mn) and deposited to a thickness of approximately $2.7\;{\AA}$ on r-$Al_2O_3$(1102) substrates by pulsed laser deposition. The r-$Al_2O_3$(1102) substrates with atomic steps and terrace surface were obtained by thermal annealing. Samples of $Ti_{0.94}Fe_{0.06}O_2$(TiFeO), $Ti_{0.94}Mn_{0.06}O_2$(TiMnO), and $Ti_{0.94}(Fe_{0.03}Mn_{0.03})O_2$ show a low remanent magnetization and coercive field, as well as superparamagnetic features at room temperature. On the other hand, superlattice films (TiFeO/TiMnO) show a high remanent magnetization and coercive field. An anomalous Hall effect in superlattice films exhibits hysisteresis loops with coercivities corresponding to those in the ferromagnetic Hysteresis loops. The superlattice films composed of alternating layers of $Ti_{0.94}Fe_{0.06}O_2$ and $Ti_{0.94}Mn_{0.06}O_2$ exhibit intrinsic ferromagnetic properties for dilute magnetic semiconductor applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.429-429
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• 2007

For various applications of liquid crystal displays (LCDs), the uniform alignment of liquid crystal (LC) molecules on treated surfaces is significantly important. Generally, a rubbing method has been widely used to align the LC molecules on polyimide (PI) surfaces. Rubbed PI surfaces have suitable characteristics, such as uniform alignment. However, the rubbing method has some drawbacks, such as the generation of electrostatic charges and the creation of contaminating particles. Thus, we strongly recommend a non contact alignment technique for future generations of large high-resolution LCDs. Most recently, the LC aligning capabilities achieved by ultraviolet and ion-beam exposures which are non contact methods, on diamond-like carbon (DLC) inorganic thin film layers have been successfully studied because DLC thin films have a high mechanical hardness, a high electrical resistivity, optical transparency, and chemical inertness. In addition, nitrogen-doped DLC (NDLC) thin films exhibit properties similar to those of the DLC thin films and a higher thermal stability than the DLC thin films because C:N bonding in the NDLC thin filmsis stronger against thermal stress than C:H bonding in the DLC thin films. Our research group has already studied the NDLC thin films by an ion-beam alignment method. The $SiN_x$ thin films deposited by plasma-enhanced chemical vapor deposition are widely used as an insulation layer for a thin film transistor, which has characteristics similar to those of DLC inorganic thin films. Therefore, in this paper, we report on LC alignment effects and pretilt angle generation on a $SiN_x$, thin film treated by ion-beam irradiation for various N ratios

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.74-74
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• 2010

One-dimensional nanosturctures such as nanowires and nanotube have been mainly proposed as important components of nano-electronic devices and are expected to play an integral part in design and construction of these devices. Silicon carbide(SiC) is one of a promising wide bandgap semiconductor that exhibits extraordinary properties, such as higher thermal conductivity, mechanical and chemical stability than silicon. Therefore, the synthesis of SiC-based nanowires(NWs) open a possibility for developing a potential application in nano-electronic devices which have to work under harsh environment. In this study, one-dimensional nanowires(NWs) of cubic phase silicon carbide($\beta$-SiC) were efficiently produced by thermal chemical vapor deposition(T-CVD) synthesis of mixtures containing Si powders and hydrocarbon in a alumina boat about $T\;=\;1400^{\circ}C$ SEM images are shown that the temperature below $1300^{\circ}C$ is not enough to synthesis the SiC NWs due to insufficient thermal energy for melting of Si Powder and decomposition of methane gas. However, the SiC NWs are produced over $1300^{\circ}C$ and the most efficient temperature for growth of SiC NWs is about $1400^{\circ}C$ with an average diameter range between 50 ~ 150 nm. Raman spectra revealed the crystal form of the synthesized SiC NWs is a cubic phase. Two distinct peaks at 795 and $970\;cm^{-1}$ over $1400^{\circ}C$ represent the TO and LO mode of the bulk $\beta$-SiC, respectively. In XRD spectra, this result was also verified with the strongest (111) peaks at $2{\theta}=35.7^{\circ}$, which is very close to (111) plane peak position of 3C-SiC over $1400 ^{\circ}C$ TEM images are represented to two typical $\beta$-SiC NWs structures. One is shown the defect-free $\beta$-SiC nanowire with a (111) interplane distance with 0.25 nm, and the other is the stacking-faulted $\beta$-SiC nanowire. Two SiC nanowires are covered with $SiO_2$ layer with a thickness of less 2 nm. Moreover, by changing the flow rate of methane gas, the 300 sccm is the optimal condition for synthesis of a large amount of $\beta$-SiC NWs.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.130.2-130.2
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• 2013

Today, chemical vapor deposition (CVD) of hydrocarbon gases has been demonstrated as an attractive method to synthesize large-area graphene layers. However, special care should be taken to precisely control the resulting graphene layers in CVD due to its sensitivity to various process parameters. Therefore, a facile synthesis to grow graphene layers with high controllability will have great advantages for scalable practical applications. In order to simplify and create efficiency in graphene synthesis, the graphene growth by thermal annealing process has been discussed by several groups. However, the study on growth mechanism and the detailed structural and optoelectronic properties in the resulting graphene films have not been reported yet, which will be of particular interest to explore for the practical application of graphene. In this study, we report the growth of few-layer, large-area graphene films using rapid thermal annealing (RTA) without the use of intentional carbon-containing precursor. The instability of nickel films in air facilitates the spontaneous formation of ultrathin (<2~3 nm) carbon- and oxygen-containing compounds on a nickel surface and high-temperature annealing of the nickel samples results in the formation of few-layer graphene films with high crystallinity. From annealing temperature and ambient studies during RTA, it was found that the evaporation of oxygen atoms from the surface is the dominant factor affecting the formation of graphene films. The thickness of the graphene layers is strongly dependent on the RTA temperature and time and the resulting films have a limited thickness less than 2 nm even for an extended RTA time. The transferred films have a low sheet resistance of ~380 ${\Omega}/sq$, with ~93% optical transparency. This simple and potentially inexpensive method of synthesizing novel 2-dimensional carbon films offers a wide choice of graphene films for various potential applications.