• 제목/요약/키워드: Electronic circuit

검색결과 3,005건 처리시간 0.027초

연산 모듈의 결합에 의한 $GF(2^m)$상의 병렬 승산 회로의 설계 (Design of Parallel Multiplier Circuit synthesized operation module over $GF(2^m)$)

  • 변기영;김흥수
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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    • pp.268-273
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    • 2002
  • In this paper, a new parallel multiplier circuit over $GF(2^m)$ has been proposed. The new multiplier is composed of polynomial multiplicative operation part and modular arithmetic operation part, irreducible polynomial operation part. And each operation has modular circuit block. For design the new proposed circuit, it develop generalized equations using frame each operation idea and show a example for $GF(2^m)$.

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A New Approach for Built-in Self-Test of 4.5 to 5.5 GHz Low-Noise Amplifiers

  • Ryu, Jee-Youl;Noh, Seok-Ho
    • ETRI Journal
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    • 제28권3호
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    • pp.355-363
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    • 2006
  • This paper presents a low-cost RF parameter estimation technique using a new RF built-in self-test (BIST) circuit and efficient DC measurement for 4.5 to 5.5 GHz low noise amplifiers (LNAs). The BIST circuit measures gain, noise figure, input impedance, and input return loss for an LNA. The BIST circuit is designed using $0.18\;{\mu}m$ SiGe technology. The test technique utilizes input impedance matching and output DC voltage measurements. The technique is simple and inexpensive.

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부분등가회로모델을 이용한 매립형 인덕터의 특성 연구 (Characterization of Embedded Inductors using Partial Element Equivalent Circuit Models)

  • 신동욱;오창훈;이규복;김종규;윤일구
    • 한국전기전자재료학회논문지
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    • 제16권5호
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    • pp.404-408
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    • 2003
  • The characterization for several multi-layer embedded inductors with different structures was investigated. The optimized equivalent circuit models for several test structures were obtained from HSPICE. Building blocks are modeled using Partial element equivalent circuit method. The mean and the standard deviation of model parameters were extracted and predictive modeling was performed on different test structure. From this study, the characteristic of multi-layer inductors can be predicted.

커패시터 커플링 노이즈를 줄인 단일 전원 CMOS 베타선 센서 회로 설계 (Design of Single Power CMOS Beta Ray Sensor Reducing Capacitive Coupling Noise)

  • 김홍주;차진솔;황창윤;이동현;;박경환;김종범;하판봉;김영희
    • 한국정보전자통신기술학회논문지
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    • 제14권4호
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    • pp.338-347
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    • 2021
  • 본 논문에서는 DB하이텍 0.18㎛ CMOS 공정을 이용하여 진성난수 생성기에 사용되는 베타선 센서 회로를 설계하였다. CSA 회로는 PMOS 피드백 저항과 NMOS 피드백 저항을 선택하는 기능, 50fF과 100fF의 피드백 커패시터를 선택하는 기능을 갖는 회로를 제안하였다. 그리고 펄스 셰이퍼(pulse shaper) 회로는 비반전 증폭기를 이용한 CR-RC2 펄스 셰이퍼 회로를 사용하였다. 본 논문에서 사용한 OPAMP 회로는 이중 전원(dual power) 대신 단일 전원(single power) 사용하고 있으므로 CR 회로의 저항과 RC 회로의 커패시터의 한쪽 노드는 GND 대신 VCOM에 연결한 회로를 제안하였다. 그리고 펄스 셰이퍼의 출력신호가 단조 증가가 아닌 경우 비교기 회로의 출력 신호가 다수의 연속된 펄스가 발생하더라도 단조 다중발진기(monostable multivibrator) 회로를 사용하여 신호 왜곡이 안되도록 하였다. 또한 CSA 입력단인 VIN과 베타선 센서 출력단을 실리콘 칩의 상단과 하단에 배치하므로 PCB trace 간의 커패시터 커플링 노이즈(capacitive coupling noise)를 줄이도록 하였다.

래치-업 면역과 높은 감내 특성을 가지는 LIGBT 기반 ESD 보호회로에 대한 연구 (Analysis of the LIGBT-based ESD Protection Circuit with Latch-up Immunity and High Robustness)

  • 곽재창
    • 한국전기전자재료학회논문지
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    • 제27권11호
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    • pp.686-689
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    • 2014
  • Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

자기인가회로를 이용한 자속구속형 초전도한류기의 고장전류제한 특성 분석 (Analysis on Fault Current Limiting Characteristics of Flux-Lock Type SFCL Using Magnetic Flux Application Circuit)

  • 고주찬;임승택;임성훈
    • 한국전기전자재료학회논문지
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    • 제30권1호
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    • pp.37-41
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    • 2017
  • In this paper, the fault current limiting characteristics of the flux-lock type SFCL (superconducting fault current limiter) using magnetic application circuit were analyzed. The flux-lock type SFCL has the structure to install the magnetic application circuit, which can increase the resistance of HTSC ($high-T_C$ superconducting element comprising) the SFCL. To analyze the fault current limiting effect of the flux-lock type SFCL through the magnetic flux application circuit, the flux-lock type SFCL either with the magnetic flux circuit or without the magnetic flux circuit was constructed and the fault current limiting characteristics of the SFCL were compared each other through the short-circuit tests.

전자혈압강하기의 전기적 특성 분석 (An Electrical Characteristics Analysis of Electronic Blood Pressure Depressor)

  • 이권순;서진호;이진우
    • 동력기계공학회지
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    • 제10권1호
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    • pp.83-89
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    • 2006
  • Recently, the seriousness of high blood pressure was appeared as the most frequent disease of a the whole sickness in the world. However, the treatment of this disease is uncertain and produces an adverse reaction of a medicine therapy. Also, the patients are burdened with a fee for medical treatment. Therefore, in this paper, we studied effectively and financially to execute the treatment of high blood pressure using the Chinese medicine theorem that is recently arousing the great interest of the people. The main theories in this paper are blood vessel theory and acupuncture, respectively. Especially, the composed circuit systems are classified the blood pressure depressor part and the meridian points discrimination part, respectively. The blood pressure depressor part is composed generally of low-frequency generation circuit, charging-discharging circuit, and micro-computer circuit. Finally, this research have the advantage of discrimination parts such as regular voltage generating circuit, stimulus circuit, amplifying circuit, and alarm circuit.

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역률개선 및 고조파 저감을 위한 전자식 안정기 설계 (Electronic Ballast Design for Power Factor Improvement and Harmonic Reduction)

  • 이충식;조문택;나승권
    • 한국항행학회논문지
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    • 제18권5호
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    • pp.483-489
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    • 2014
  • 제안된 회로는 교류 입력 전원부와 무손실 스너버 회로가 부가된 DC-DC 컨버터와 DC-AC 변환을 위한 인버터로 구성하였다. 변환된 등가회로를 이용하여 형광램프의 특성을 만족시킬 수 있는 최적의 회로상수를 결정해서 설계함으로써 기존의 인버터 직류측에서 발생되는 맥동주파수에 의한 왜형파 발생을 제거하고 인버터의 입력전류를 불연속이 되도록 하므로써 맥동율과 스위칭 손실을 현저히 감소시켰다. 이러한 모든 결과를 증명하기 위하여 40 W 직관형 형광램프를 대상으로 실험하여 고조파의 발생을 측정한 결과 제안된 전자식 안정기의 우수성을 확인하였다.

전자 저울을 위한 지능형 고장 진단 시스템 (Intelligent Diagnosis System for an Electronic Weighting Machine)

  • 김종원;김영구;조현찬;서화일;김두용;이병수
    • 한국지능시스템학회:학술대회논문집
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    • 한국퍼지및지능시스템학회 2001년도 추계학술대회 학술발표 논문집
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    • pp.78-82
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    • 2001
  • Electronic Weighting Machine is used an electronic scale which has many trouble because of broken load cells. In this paper, we propose an intelligent Diagnosis System will for an electronic weighting machine using fuzzy logic. It's purpose be detect of the load cell's trouble. The electronic circuit of system, which call 'junction box', will be connected resistances in a series at circuit of Wheatstone Bridge for monitoring the condition of load cells.

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Electronic Dash-pot System Development for Power Electronic Circuit Protection using the Current Sensor

  • Kim, Chul-Ki;Ryu, Jae-Heun;Yoon, Dal-Hwan
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 ITC-CSCC -3
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    • pp.1401-1403
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    • 2002
  • This paper presents the development of an electronic dash-pot(EDP) system it)r protecting the power electronic circuit. The EDP play role protecting an equipment by disconnecting between voltage source and load system. Also, converting the existed electrical system into an electronic mechanism, it can reduce the power consumption and prevents the system damage due to over current.

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