• The Journal of the Korea institute of electronic communication sciences
• /
• v.17 no.2
• /
• pp.351-356
• /
• 2022

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.459-460
• /
• 2008

In this paper, a 10Gbps clock and data recovery circuit is designed in $0.18{\mu}m$ CMOS technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a charge pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.2ps and a peak-to-peak recovered data jitter of 8ps while consuming about 80mW from a 1.8V supply.

• 제어로봇시스템학회:학술대회논문집
• /
• 1992.10b
• /
• pp.245-250
• /
• 1992

In this paper, we present a nev algorithm for the fast computation of the discrete cosine transform(DCT). This algorithm consists of the three dimensional prime factor-decomposed algorithm(PFA) and three dimensional common factor-decomposed algorithm(CFA). We can compute N-point DCT for the number N decomposable Into three relative prime numbers using PFA and into three common numbers using CFA. We also show input and output index mapping for the three decomposition. it results in requiring fever multiplicaions than the previous algorithms. Particularly, for the large number N, it is more powerful in reducing the number of multiplication.

• Journal of the Optical Society of Korea
• /
• v.13 no.3
• /
• pp.386-391
• /
• 2009

PSPICE circuit parameters of the blue laser diodes grown on wurtzite AlGaInN multiple quantum well structures were extracted directly from the three level rate equations. The relevant optical gain parameters were separately calculated from the self-consistent multiband Hamiltonian. The resulting equivalent circuit model for a blue laser diode was schematically presented, and its modulation characteristics, including the pulse response and the frequency response, have been demonstrated by using a conventional PSPICE.

• Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
• /
• 1998.11a
• /
• pp.156-161
• /
• 1998

The purpose of this paper is to determine circuit parameters in the inverter part of the electronic dimming ballast for fluorescent lamps, that is adequate to use with the prevailing dimming controller IC. Firstly, the operating frequency characteristics are investigated by varying circuit parameters of electronic ballasts and are matched with the output characteristics of dimming ballast controller. Secondly, circuit parameter values are determined by using PSpice simulation and operating frequency characteristics. Finally its validity is verified from the electrical and light output characteristics on the prototype of the electronic dimming ballast.

• Proceedings of the KIEE Conference
• /
• 2007.10a
• /
• pp.197-198
• /
• 2007

In this paper, a 10Gbps Clock and Data Recovery circuit is designed in $0.18{\mu}m$ CMOS Technology. The circuit incorporates a multiphase LC oscillator, a quarter-rate Bang-Bang phase detector, a Charge Pump and a second order loop filter. The simulation results show that the designed circuit has a peak-to-peak clock jitter of 4.1ps and a peak-to-peak recovered data jitter of 8ps while consuming about 44mW from a 1.8V supply.

• Journal of Power Electronics
• /
• v.6 no.4
• /
• pp.330-339
• /
• 2006

This paper deals with novel electronic ballast based on single-stage power processing topology using a symmetrical half-bridge inverter and current injection circuit. The half-bridge inverter drives the output parallel resonant circuit and injects current through the power factor correction (PFC) circuit. Because of high frequency current injection and high frequency modulated voltage, the proposed circuit maintains the unity power factor (UPF) with low THD even under wide variation in ac input voltage. This circuit needs minimum and lower sized components to achieve the UPF and high efficiency. This leads to an increase in reliability of ballast at low cost. Furthermore, to reduce cost, the electronic ballast is designed for two series-connected fluorescent lamps (FL). The analysis and experimental results are presented for ($2{\times}36$ Watt) fluorescent lamps operating at 50 kHz switching frequency and input line voltage (230 V, 50 Hz).

• Journal of Electrical Engineering and Technology
• /
• v.11 no.2
• /
• pp.416-424
• /
• 2016

In this study, automatic detection of stator winding inter-turn short circuit fault (SWISCFs) in surface-mounted permanent magnet synchronous motors (SPMSMs) and automatic classification of fault severity via a pattern recognition system (PRS) are presented. In the case of a stator short circuit fault, performance losses become an important issue for SPMSMs. To detect stator winding short circuit faults automatically and to estimate the severity of the fault, an artificial neural network (ANN)-based PRS was used. It was found that the amplitude of the third harmonic of the current was the most distinctive characteristic for detecting the short circuit fault ratio of the SPMSM. To validate the proposed method, both simulation results and experimental results are presented.

• Journal of the Semiconductor & Display Technology
• /
• v.17 no.1
• /
• pp.21-26
• /
• 2018

In this paper, a multiple coupling inductor with expandable-integrated magnetic structure was proposed to enable miniaturization of external switched mode power supply (SMPS) for a large display. Inductance formula of the proposed inductor structure was derived through magnetic circuit analysis for a simple inductance designing process. The proposed inductor was applied into a 1kW class interleaved bridgeless power factor correction circuit which requires four inductors, and experimental steady state result of the circuit was compared. According to the experimental result, it was found that the proposed multiple coupling inductor shows the electrical characteristics that can replace the conventional separated inductors and is suitable for miniaturization of the SMPS since the circuit configuration is possible with one shared inductor.

• The Transactions of the Korean Institute of Power Electronics
• /
• v.25 no.6
• /
• pp.503-510
• /
• 2020

The importance of DC breakers as key protection equipment is increasing in accordance with growing concerns on MVDC distribution network systems without DC/AC conversion. Different from the situation in AC systems, no natural zero-crossing point exists in DC systems. Thus, DC breaker technology is more difficult than AC breaker technology. The solutions for DC breakers can be divided into three types: mechanical, power electronics, and hybrid. In this study, the operating principles of several topologies of hybrid circuit breakers and that of the proposed DC breaker are analyzed and simulated by sorting two types. The breakers are compared in terms of the type and number of semiconductors, volume, power loss, auxiliary components, isolation, and other aspects. The advantages and disadvantages of the breakers are also analyzed.